The difference is that while triggering on edge, you get one short pulse as trigger, while using level triggered the duration of that pulse is as long as the level is 'high' (or 'low', depending on what you are triggering).
Latch is an asynchronous sequential device that watches all of its inputs continuously and changes its outputs’ state at any time, if a special signal (commonly noted as E, i.e. enable) is asserted. Flip-flop is a synchronous sequential device that normally samples its inputs and changes its outputs only at times determined by the active edge of a clocking signal C (clock).[/i]
D-trigger has only one data input D (Delay). The logic level of this input transfers to the output only after clock signal. In fact, the D-trigger is the basic memory cell. It is known as D-trigger because of the fact, that its output receives the input value on the next clock cycle, i.e. after some delay (one clock cycle).
The next figure shows a gated D-trigger. Such structure is used in the major part of parallel registers, as the monolithic IC ‘373.
If a dynamic SR-trigger is used, a dynamic D-trigger can be realized. This is shown in the next figure, and this structure is used in monolithic IC ’74.
The dotted lines show additional inputs for asynchronous reset and set signals.
level trigger is done.. uh .. well.. as long as the signal maintains the voltage level it's supposed to trigger
Edge triggering happens not on a level but on transition between levels, or specifically either or on both of falling and/or rising edge of the signal.