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What is the difference between score board and checker in System Verilog?

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Jun 4, 2011
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what is the difference between score board and checker?

Re: About System verilog

this book has it all..
UVM/OVM - Mentor Graphics

a scoreboard is a mechanism for tracking which tests and which requirements have been run/verified.
For example, a testbench may have multiple tests which verify multiple requirements (not often in 1:1 correspondence either). A portion of the overall testbench is to capture and record the success/failure of each test, and/or requirement verified. This is the purpose of the scoreboard.

Another aspect of good verification is to segregate interface specification verification from performance specification verification.
For example you could create a protocol checker that monitors an interface and verifies that each transaction on that interface is per
the protocol on the interface. But to keep it portable, that protocol checker would not verify specific contents of transactions, that is
done elsewhere (so the content checker can be portable across different interfaces too).

In simple words
A Scoreboard is used to keep track of how many transactions were initiated, how many finished and how many are pending and whether a given transaction passed or failed.
A checker is used to check whether a given transaction has taken place correctly . This may include data correctness and correct signalling order.
Re: About System verilog

But i tried writing the pass/fail code in checker its getting displayed... I thought in checker v mainly display things but tat could also be done in checker so i wanted to know the precise difference sir..

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