What is the difference between reg and wire?

[weng]

reg & wire

Hi,

What is the difference between reg and wire? When should we use reg and when should we use wire?

 

[linuxluo]

Re: reg & wire

hi,
it's just a data type . if you want to generate a reg you have to set this type to your signal. normally, the output of always block is reg type.

 

[yuenkit]

Re: reg & wire

the reg in verilog is not register, the name is confusing.

let me explain the difference between reg and wire.

int *a,
&a = 4;
int *b,
&b = a;
&a = 7;,

then &b = 7;

wire is analogue to the above c assignment, if the value of source change, the value of wire will change as well.

int a;
a = 4;
int b;
b = a;
a = 7;

then b = 4;

reg is analogue to above assignemnt, once the assignment done, there is no conne ction between the source and the reg.

Correct me if my syntax is wrong. I have no time to verify the C syntax

 

[nand_gates]

Re: reg & wire

here are few points!
1. wire gets initialize by default to 'z' whereas reg gets initialize to 'x'
2. wire does not hols previous value where as reg holds old value if not diven.
3. wire can not be driven inside always whereas registers generally deiven inside
always block!

 

[dr.farnsworth]

Re: reg & wire

easy way of remembering :idea:

connection rules:
-----------------------------------------------------------------------------

• port type=input

• internally=net

• externally=reg or net

• port type=output

• internally= net or reg

• externally= net

• port type=inout

• internally= net

• externally= net

-----------------------------------------------------------------------------
the net data type is defined as wire


regards,
Dr.farnsworth

 

[r_p_sanna]

reg & wire

wire synthysis to a combinational logic while Reg synthysis to a Sequential logic

Added after 42 minutes:

http://www.sunburst-design.com/papers/CummingsHDLCON2000_RegProposal.pdf

a paper by clifford cummings. hope this helps u understand about register data types a little more

 

[AlexWan]

reg & wire

"wire" is only used in "assign" or connect.
"reg" is for latch or register type.

 

[weng]

Re: reg & wire

How about in terms of synthesis?

What will a reg type or a wire type looks like when synthesize? What are the difference?

 

[yuenkit]

Re: reg & wire

wire -> net & wire.
reg -> difficult to say, maybe generated to latch or flipflop, or memory block.

 

[carrot]

Re: reg & wire

Hi,

Whenever you want to store a value, then you have to use reg.
But when you just want to pass the value to the next logic element then you can use wire.

reg comes into play when we design sequential elements
wire is used both in sequential and combinational

 

[pra]

reg & wire

For example
if u want to write a behavioral code for a D flipflop
u require where u r getting input D from a nand gate then

u shud write reg at the o/p pin of the flipflop for storing the value
and u require wire at the o/p pin of nand gate.

 

[test_out]

reg & wire

reg is used when you want to keep the value of variable until next time its be change. input and inout cant be reg. reg is only for output.

wire is the other term of net. wire can be input, output, inout.

Wish this make you clear!

 

[deva_eda]

reg & wire

Simple golden rules :

1. A reg data cannot be used for assign statement . It should be wire

2. All the variables being computed in the always block should be of data type reg, they cannot be wire.