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What is the difference between reg and bit type variable with respect to VERA?

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shiv_emf

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Hello

what is the difference between reg and bit type variable with respect to VERA lanuage...
when verilog task r called frm vera testbench ..... hdl_task is declared in vera testbench ...n in this case... what shud be variable type of parameters of verilog task ?

bit or reg?
Shiv
 

ankit12345

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bit and reg

there is no diff b/w bit n reg in vera,.....................
second question......my tool is not supporting.........so no comments.
 

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