What is the difference between "posedge reset" and

[Blilix]

I start learning Verilog for ASIC design. I am confused between "posedge reset" and "reset" when I want to create the D-FF with asynchronous reset. Could anybody explain this for me? I saw some textbooks using "posedge reset" but some using only "reset" in "always" statement to create D-FF.

Thank you

 

[rjainv]

before that, its important to understand that there are two kinds of always statements in verilog
1) sequential, it has edge sensitivities ( (pos|neg)edge clk, and optionally (pos|neg)edge reset or preset or both.
2) combinatorial block, having all level sensitive inputs of combo in sensitivity list.

If you use 1) and write like this,

always( posdedge clk or posdedge reset ) begin
if ( reset)
var <= 1'b0;
else
something intereseting...


then you are modelling an asynchronous reset, as reset is a triggering event for the always block.


if you don't list the reset in sensitivity list, even though you assert reset, flop will get reset only on arrival of clk. Hence its synchronous reset.


2) If you use reset here, then essentially you are using it as data input. Again its supposed to be synchronous...