What is the difference between logical and physical mapping for a library in ModelSim

[matrixofdynamism]

When we use ModelSim, we can create a project and a library. These two are different things. A project shall be a folder containing all files for our project. A library is where the files we have compiled into ModelSim specific proprietery intermediate language shall be stored. Is this correct?

Now within the project folder we shall have a folder for library files. This folder is usually named "work", as a convention.

Within ModelSim though we name 2 things, we name the library "physical mapping" which is name of the folder within project directory that shall contain our library files, and library "logical mapping" which is name of the library as appears from within ModelSim along with all the other libraries.

Why do we have these 2 levels? I am sure a physical mapping is sufficient. Why do we need to have logical mapping as well which I think is stored into modelsim.ini?

 

[ads-ee]

Physical mapping is where does the modelsim library exist on the system, i.e. the directory where the library was compiled.
Logical mapping is the name the library has when used by -L or when used in the use library_name in VHDL.

So basically if you compile all the library code into the directory ./my_library_of_yada_yada_bazinga (physical) you can logically map it to a library called xyz_lib if you want. You can find those physical to logical mappings in the .prj or .ini file.

The project is just Modelsim's way of handing your source files. The logical library mapping, I think (might be completely wrong), are from Modelsim's roots as a VHDL only simulator (though I can't find any history on that subject), as VHDL uses libraries with a use library_name;, those libraries need to have a specific name (hence the logical name) which is translated from the physical directory name.

Verilog simulators don't have "libraries" so simulators like VCS, Verilog-XL don't have to do any translations they just need to know the location of the compiled/pre-compiled design files.

 

[dave_59]

ads-ee, you are correct, the physical/logical library mapping comes as a requirement for VHDL to be able to write source code that is implementation independent. File pathnames introduce OS specific information, so the logic names are used in their place.

ModelSim as well as NCsim introduced a separate compilation flow and the use of libraries to Verilog, and the library concept was incorporated into the Verilog-2001 standard along with VHDL-like configurations. VCS just recently introduced separate compilation to its flow.

ModelSim project directories are specific to the ModelSim Graphical User Interface and are a way to collect all of the information about running a simulation in a single directory (source files, option settings, etc). It is certainly possible to have a project reference libraries that are from other projects or not even specific to a project. (Don't ask me how).

 

[ads-ee]

ModelSim as well as NCsim introduced a separate compilation flow and the use of libraries to Verilog, and the library concept was incorporated into the Verilog-2001 standard along with VHDL-like configurations. VCS just recently introduced separate compilation to its flow.

I wasn't really aware that this was the case as I've read most of the LRM but didn't dwell on the non-synthesizable and non-useful testbench stuff.

I've never used configurations even when I used to use VHDL, so their addition to Verilog I just completely ignored.

 

[dave_59]

Configurations and libraries are certainly used with synthesizable code, albeit not much.