what is the difference between initial and always in verilog

[preethi19]

can anyone tell me the difference between initial and always block.... it was put initial block initializes variables for simulation and its not synthesizable... what is the need to initialize variables... initializing variables does that mean we assign a value to the variable??? ok suppose take an and gate... we declare the input variables a and b.... so like now i want to assign values to these variables... we use assign keyword to just assign the condition right ie (a & b). to assign the values do we use intial blocks??? then wat is always block used for.... do we assign condition using assign or always block??? like if initial and always block are same then why do we use an initial block and is initial and always block dependent on each other like wer the always block conditions gets its variable values assigned in initial block.... sorry if i am wrong but totally confused.. pls help

 

[kornukhin]

Both Initial and Always are procedural blocks, but:
- Initial executes once upon simulation starts (it is not synthesizable and used for tests, to set initial values of variables in simulation (by default variables have unknown(x) value at start up) )
- Always executes every time control event happend (ex., rising edge of 'clk' signal in 'always@(posedge clk)). Some of the construct synthesizable, but some aren't. Synthesizable 'always' subset defined in Verilog LRM IEEE 1364-2002.

 

[preethi19]

oh thank you for the reply... so i understand initial and always block... but don't we need to set the initial value for the system that is being synthesized??? in the sense see the following eg

initial clk=1b'0;
always
#(period/2)clk=~clk;
initial #100 $finish;

(the period parameter is set to 50)

i understand clk value is set to 0 initially. and this value is like inverted with a delay by the always block and ends at the time interval 100. so from above eg we can see always block is dependent on initial block for the value to start??? so do we always need an "initial" block before "always" block??? because i saw in other eg there was no initial block but only always block was used... so in this case if the condition needs to work on a variable how can it be executed without a variable being set through the initial block...
AND also why do we need initial #100 $finish to end the loop.. can we specify a terminating condition within the always block itself without using initial again?? pls help....

 

[ads-ee]

The code you have isn't for synthesis. It's testbench code to generate a clock and run a simulation for 100 time units.
Don't recall where I read that the best way to generate a testbench clock is with the following code:

initial begin
  clk = 0;
  forever #(period/2) clk = ~clk;
end

 

[dave_59]

Two reasons its better to use an initial block to generate a clock

initial begin
  clk = 0; // 1. you can control the initial state of the clock
  #phase // 2. you can add a phase delay
  forever #(period/2) clk = ~clk;
end