Both Initial and Always are procedural blocks, but:
- Initial executes once upon simulation starts (it is not synthesizable and used for tests, to set initial values of variables in simulation (by default variables have unknown(x) value at start up) )
- Always executes every time control event happend (ex., rising edge of 'clk' signal in 'always@(posedge clk)). Some of the construct synthesizable, but some aren't. Synthesizable 'always' subset defined in Verilog LRM IEEE 1364-2002.