What is the difference between Classes and Modules in System Verilog?

[kunal1514]

Hi All,

Can any body tell me that What is the difference between Classes and Modules in System Verilog

 

[aji_vlsi]

Re: Classes and Modules

Hi All,

Can any body tell me that What is the difference between Classes and Modules in System Verilog

This is a big topic, search in verificationguild.com for detailed replies. I also cover this in our "Verification using SystemVerilog" course in Bangalore!

Ajeetha, CVC
www.noveldv.com

 

[akmnazrul]

Can any body tell me that What is the difference between Classes and Modules in System Verilog

Answer: Class is composed of set of members that describe how an instance of class or object is constructed and how it behaves.Example: class class name{ member1; ---------------} object name;
On the other hand: The module is the basic building block in verilog which is used in creating a design. Systemverilog adds a new block called program block which can be declared using the keywords program and end program.

 

[dave_59]

Hi All,

Can any body tell me that What is the difference between Classes and Modules in SystemVerilog

Yes, there are many people that can tell you the difference. ;-)

But you may not understand the answer. It would help to know what your experience is with Verilog and other programming languages so we can explain it or point you other resources that you would understand.