This is a big topic, search in verificationguild.com for detailed replies. I also cover this in our "Verification using SystemVerilog" course in Bangalore!
Answer: Class is composed of set of members that describe how an instance of class or object is constructed and how it behaves.Example: class class name{ member1; ---------------} object name;
On the other hand: The module is the basic building block in verilog which is used in creating a design. Systemverilog adds a new block called program block which can be declared using the keywords program and end program.
Yes, there are many people that can tell you the difference. ;-)
But you may not understand the answer. It would help to know what your experience is with Verilog and other programming languages so we can explain it or point you other resources that you would understand.