[SOLVED] What is the difference between BUFFER and OUT in VHDL?

Status
Not open for further replies.

iVenky

Advanced Member level 2
Joined
Jul 11, 2011
Messages
584
Helped
37
Reputation
76
Reaction score
35
Trophy points
1,318
Location
College Station, Texas
Activity points
6,124
Hello everyone. I am new to VHDL. I want to know the difference between BUFFER and OUT because both look similar.


Thank you in advance
 

out: the value of an output port can only be updated within the entity model; it cannot be read.
buffer: the value of a buffer port can be read and updated within the entity model. However, it differs from the inout mode in that it cannot have more than one source and that the only kind of signal that can be connected to it can be another buffer port or a signal with at most one source.

VHDL Primer by J. Bhasker is a good book to start with.
 
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…