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What is the difference between "<=" and "=" in Verilog?

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bcdeepak

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i am new to verilog
plz clear my doubt ..........

to assign something we have to use .....

assign b <= ' 0 '

and when should we use simply b<= ' 0 ' ??????????


and one more doubt .............

what is the difference between " <= " and " = " ?????????

eg :

a <= ' 0 ' and a= ' 0 '
 

darylz

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verilog doubt

What you need is a reference book for beginner, I think this book is helpful for you:



or
 

bcdeepak

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Re: verilog doubt

to check condition , i think we have to use a==' 0 ' ??????
 

no_mad

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verilog doubt

Hi,

Please check out the link below:


Someone already submit same question here.
Please read my reply. Let me know if u still have questions.
 

YenYu

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Re: verilog doubt

Check out this...
It will gif u more ideas about the operators and more...
 

bcdeepak

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Re: verilog doubt

thanks
i got blocking and non-blocking differece .

my another doubt is ...

if we want to assign some value ........ when should we use

assign b <= ' 0 '

and when we can use simply like b <= " 0 '

i mean when the word " assign " should be used and when it should not be used ??????????

assign out = a & b;
or
always @(a or b)
begin
out = a & b;
end

in the above eg , why once " assign out = a & b; " is use and another time simply " out = a & b; " is used
 

dinaganesh

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Re: verilog doubt

hi friend !!

assign a = <expression >; is the assigning operator in VERILOG

only in VHDL it comes as a <= <expression >;
 

omara007

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verilog doubt

as a procedural assignment , you can use assign and you may not use it .. but outside the procedure (always or initial) you can't assign a value to a signal without useing (assign)
 

jason99pan

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Re: verilog doubt

bcdeepak said:
thanks
i got blocking and non-blocking differece .

my another doubt is ...

if we want to assign some value ........ when should we use

assign b <= ' 0 '

and when we can use simply like b <= " 0 '

i mean when the word " assign " should be used and when it should not be used ??????????

assign out = a & b;
or
always @(a or b)
begin
out = a & b;
end

in the above eg , why once " assign out = a & b; " is use and another time simply " out = a & b; " is used

=================================================
Hi,
In my knowledge, the "assign" statement is a "Procedural Continuous assignment".

For example, the output of a transparent latch will follow the data input when the latch is enabled, but when the latch is disabled, it must ignoew any changes on its data input and retain its last output value until it is again enable.

I think the "assign" statement models this behavior.

Maybe It will be useful for you.
 

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