What is the delta delay in RTL ?

[megastar007]

what is delta delay in RTL ?

 

[Jyotshna Mamillapalli]

Re: Delta Delay

I have heard of transisition delay and inertial delay.

May I know, where have you come across this delay?

 

[xstal]

Re: Delta Delay

what is delta delay in RTL ?

This delay is releted to simulation of HDL code, also known as simulation deltas. The simulation time is divided into small periods i.e. delta,

when a signal is assigned a value, the value of the signal is not immediately altered but it is only scheduled to be assigned at the end of the process. The process takes one delta for one cycle hence the signal is assigned its scheduled value after one simulation delta delay. This delay has nothing to do with the real hardware, it is only tool software feature.

 

[Jyotshna Mamillapalli]

Re: Delta Delay

yes.

In simulation, after getting wave forms, how can we see this dellta delay?

And is delta delay equals to clock to q delay?

 

[fazal_ece]

Re: Delta Delay

it is the delay at synthesis level

 

[aji_vlsi]

Re: Delta Delay

yes.

In simulation, after getting wave forms, how can we see this dellta delay?

And is delta delay equals to clock to q delay?

VCS & MTI provide a way to do this in their GUI as: "Capture Delta Delay"

HTH
Ajeetha, CVC
www.noveldv.com

 

[Jyotshna Mamillapalli]

Re: Delta Delay

ok. fine.

Thanks a lot for the information.

 

[sumit_techkgp]

Delta Delay

This is the delay in which the simulator advnces
Sumit

 

[ripperx2]

Re: Delta Delay

Hello,
I have an advance question about delta delay.
I've developed a circuit in VHDL which does only contain combinatorial logic with an (unavoidable) internal feedback. In simulation it happens that the output signal needs 3 delta delays to stabilize.
time x+1: '1'
time x+2: '0'
time x+3: '1'
with "time x" as simulation time + delta delay. During the second delta delay my output signal has the value '0' which I don't want to have. Has somebody an idea what happens with this circuit when it is synthesized? Will the circuit operate correct or will the output signals contains this pulse from the second delta delay?
Thanks for your help!

 

[jpvSoccer]

Re: Delta Delay

Hi,

If you simulate your gate level netlist with transport delays (rather than inertial delays) you will probably see the glitch propagate through the circuit.