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what is the common synthesis methodology for large scale SOC

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richardhuang

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Hi, can anybody introduce the mothordology which you have used in SOC peoject by using DC . such as diffrect phase?top-down or bottom-up. etc. and we know DC have may inhanced version such as ultra, XG, what is the difference between them?
 

spauls

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Re: what is the common synthesis methodology for large scale

bottom-up is the best for big SoC's
 

shiv_emf

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U have to refer user guide for detailed information.
I believe most of ASIC designs follow Bottom up...

Guys can u come up with pro n cons of top-down and bottom ! searching this forum can also fetch u more info..
 

rsrinivas

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Bottom up synthesis is done so that u can characterise ur design and derive the constraints from the design.
But the final compilation with the derived constraints is Top down!!!!!

The Ultra mode supports inbuilt efficient library functions(like adders muls etc) and has a better algo to synthesise ur code in terms of area and timing but u need a seperate license for that....

Regards
 

amittewarii

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Re: what is the common synthesis methodology for large scale

Bottom Up Synthesis approach is best to apply when the SOC design size is very big


Cheers ,
Amit
 

richardhuang

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Yes, i definitely agree with the bottom-up flow. but when the tool recurse the bottom-up across the hierarchy,how does the haracterise be used for objected instances?
 

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