In any CMOS inverter, if you look close enough, you'll see
such opposing-direction perturbations precede the output
going in the eventual right direction. This is the Miller
capacitance of the FET coupling the (say) L-H gate transition
to the output, ahead of the eventual H-L drain transition.
You also have that huge taper chain's shoot-through
current and gate displacement currents banging the ground
and the supply, and through the local decoupling one of
those has a pretty strong dynamic effect on the other.
All of that spike-ery bumping against the ground inductance
to produce voltage spikes on the 'scope probe, by jacking
the reference ground (but also the MOSFET driver's internal
vs reference ground, the output will follow the on-chip
ground which has additional wire bond inductance and is
never as clean as board ground).