Mar 6, 2008 #1 P pixel Advanced Member level 2 Joined Sep 16, 2004 Messages 508 Helped 69 Reputation 138 Reaction score 16 Trophy points 1,298 Activity points 3,993 I need to create new vector of size Nbits where most sinificant bits are filled in by A(4). What is the best way to do that? A: in STD_LOGIC_VECTOR(4 downto 0); B: in STD_LOGIC_VECTOR(Nbits-1 downto 0); This works only if I know Nbits B=(A(4)&A(4)& .... A(4)&A(4)& A)
I need to create new vector of size Nbits where most sinificant bits are filled in by A(4). What is the best way to do that? A: in STD_LOGIC_VECTOR(4 downto 0); B: in STD_LOGIC_VECTOR(Nbits-1 downto 0); This works only if I know Nbits B=(A(4)&A(4)& .... A(4)&A(4)& A)
Mar 6, 2008 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,422 Helped 14,752 Reputation 29,786 Reaction score 14,101 Trophy points 1,393 Location Bochum, Germany Activity points 298,107 Re: VHDL question The most flexible way is by a FOR loop, either in a process or as a FOR GENERATE. BitGen: FOR I IN 4 TO NBITS-1 GENERATE B(I) <= A(4); END GENERATE; or PROCESS(*) BEGIN FOR I IN 4 TO NBITS-1 LOOP B(I) <= A(4); END LOOP; END PROCESS; There is also an assignment syntax with a combination of OTHERS and designated bits, but I generally don't use it.
Re: VHDL question The most flexible way is by a FOR loop, either in a process or as a FOR GENERATE. BitGen: FOR I IN 4 TO NBITS-1 GENERATE B(I) <= A(4); END GENERATE; or PROCESS(*) BEGIN FOR I IN 4 TO NBITS-1 LOOP B(I) <= A(4); END LOOP; END PROCESS; There is also an assignment syntax with a combination of OTHERS and designated bits, but I generally don't use it.
Mar 6, 2008 #3 A achandra Newbie level 5 Joined Feb 6, 2008 Messages 10 Helped 3 Reputation 6 Reaction score 0 Trophy points 1,281 Activity points 1,342 Re: VHDL question Is a statement like B=((others<=A(4))&A); supported?
Mar 6, 2008 #4 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,422 Helped 14,752 Reputation 29,786 Reaction score 14,101 Trophy points 1,393 Location Bochum, Germany Activity points 298,107 Re: VHDL question These two syntaxes are possible: B<=(nbits-1 downto 5 => A(4)) & A; B<= (others => A(4),3 => A(3), 2=>A(2),1=>A(1),0=>A(0));
Re: VHDL question These two syntaxes are possible: B<=(nbits-1 downto 5 => A(4)) & A; B<= (others => A(4),3 => A(3), 2=>A(2),1=>A(1),0=>A(0));
Mar 7, 2008 #5 P pixel Advanced Member level 2 Joined Sep 16, 2004 Messages 508 Helped 69 Reputation 138 Reaction score 16 Trophy points 1,298 Activity points 3,993 Re: VHDL question Danke schön FvM, Does verilog have equivalent to "others"?
Mar 7, 2008 #6 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,422 Helped 14,752 Reputation 29,786 Reaction score 14,101 Trophy points 1,393 Location Bochum, Germany Activity points 298,107 Re: VHDL question Verilog has no construct adequate to VHDL aggregate that was used in both examples. The expression can be written using concatenation and replication, also utilizing nbit as a length parameter.
Re: VHDL question Verilog has no construct adequate to VHDL aggregate that was used in both examples. The expression can be written using concatenation and replication, also utilizing nbit as a length parameter.