What is the Best method for Logical Synthesis, including Sub-hierarchical design?

[Collang2]

I have 4 files about sub-design.
Netlist, Block abstraction model), ETM (extracted timing model) and Black box.


I wonder which file is the best to use when Logical synthesizing(Design compiler) the top design... Maybe I should know the advantages and disadvantages of the methods.

 

[ThisIsNotSam]

I don't understand the question at all. Input to logic synthesis is RTL.