Re: Synthesis
hi
if you see vlsi design cycle,first we will define problem with some constraints,to tht we write formal description using VHDl or verilog.the written code can be used to do simulation(functional verification).,but the need is vlsi designer should provide HW.tht can be done when we do synthesis for the code written using synthesizer.
the output file of a synthesizer is a netlist consists of components and their interconnections,the component are assigned,schduled and mapped based on the code written.
important thing to note is dont expect synthesis tool to provide an optimum netlist for a worst code written.
bye find more frm other texts in the board.