what is the appropriate library for having arithmetic operation on vectors?

[fahim1]

hi
i want to do multiply and arithmatic operation on vectors,i defined the types unsigned but i still have error.i think its because of the library .i use the std_logic_arith,i dont know which part is wrong??

 

[TrickyDicky]

Post the code with the errors. Std_logic_arith is not a standard library - you should use numeric_std library, which is a VHDL standard

 

[fahim1]

Post the code with the errors. Std_logic_arith is not a standard library - you should use numeric_std library, which is a VHDL standard

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
--use IEEE.NUMERIC_STD.all; 
entity cshm is
port(x : in unsigned(3 downto 0);
  clk : in std_logic;
  res : out std_logic_vector(7 downto 0));
end cshm;
architecture cshm_arch of cshm is
  type registers is array (7 downto 0) of std_logic_vector(7 downto 0);
  signal reg0,reg1,reg2,reg3 : registers := ("000000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
  signal ena : std_logic := '0'; 
  signal res0,res1,res2,res3 : std_logic_vector(7 downto 0) := "00000000";
  constant c0 : unsigned(3 downto 0) := "0001";
  constant c1 : unsigned(3 downto 0) := "0010";
  constant c2 : unsigned(3 downto 0) := "0011";
  constant c3 : unsigned(3 downto 0) := "0100";
begin 
  process(x)
    variable i : integer range 0 to 7 := 0 ;
    variable j : integer range 0 to 3 := 0 ;
    begin 
        if (j=0) then
      reg0 <= (0001*x,0011*x,0101*x,0111*x,1001*x,1011*x,1101*x,1111*x);
    j := j+1;
  elsif (j=1) then
    reg0 <= (0001*x,0011*x,0101*x,0111*x,1001*x,1011*x,1101*x,1111*x);
    j:= j+1;
    elsif (j=2) then
    reg1 <= (0001*x,0011*x,0101*x,0111*x,1001*x,1011*x,1101*x,1111*x);
    j := j+1 ;
    elsif (j=3) then
    reg2 <= (0001*x,0011*x,0101*x,0111*x,1001*x,1011*x,1101*x,1111*x);
    elsif ( j=4 ) then 
      ena <= '1';
    end if;
    end process;

 

[FvM]

reg0 <= (0001*x,0011*x,0101*x,0111*x,1001*x,1011*x,1101*x,1111*x);

All signals involved in the arithmetic operations should have unsigned type, otherwise type casts are necessary. The array type of reg0 should be defined respectively.

0001 etc. aren't valid unsigned literals.

 

[fahim1]

tnx for answering...
what should i do to define 0001,0011,... unsigned?

 

[FvM]

reg0 <= ("0001"*x,"0011"*x,"0101"*x,"0111"*x,"1001"*x,"1011"*x,"1101"*x,"1111"*x);