sandy.vb
Newbie level 5
wildcard in vhdl
hi
what is the analogue of always(*) in vhdl? (i mean just as we write always (*) in verilog, what should we write inside the brackets in process() in vhdl? or is it that we must manually write all the signals involved inside the process block?)
thanks in advance.
hi
what is the analogue of always(*) in vhdl? (i mean just as we write always (*) in verilog, what should we write inside the brackets in process() in vhdl? or is it that we must manually write all the signals involved inside the process block?)
thanks in advance.