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what is the analogue of always(*) in vhdl?

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sandy.vb

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wildcard in vhdl

hi

what is the analogue of always(*) in vhdl? (i mean just as we write always (*) in verilog, what should we write inside the brackets in process() in vhdl? or is it that we must manually write all the signals involved inside the process block?)

thanks in advance.
 

devas

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Re: wildcard in vhdl

Hi,

process(all).

However this feature was introduced in VHDL-2008. In VHDL-87 en -93 you have to write out all signals. So you have to figure out that your simulator and synthesis tool supports this feature of VHDL-2008.

Devas
 

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