Re: what is the 0.18um means in the "taped out in .18um
another question
I synthesized one of my designs,and i am trying to calculate the gate number.
Hi,
Maybe this might help for gate count estimation...
Things you'll need are..
1. DC area report of the design
2. Library cell unit to gates conversion factor. (From ASIC vendor)
Normally, after synthesis, SCAN flops have not been inserted. So, if you will be inserting SCAN into your design, you'll need to factor this in. Typically, the increase is 25% of noncombinational logic.
From the synthesis area report, the two items that are important are
- Combinational Area (A)
- Noncombinational area (B)
1) Compute estimated total gate count of design with SCAN flops by multiplying 1.25 to the Noncombinational area (B).
2) Add result of 1 to combinational logic(A) to get total cell area.
3) Convert cell area to gates by dividing result of from step 2 by gate conversion factor.
4) result of 3 is gate count.