Hi dude,
Even if you code the design as in1<<in2, it will be converted into a combinational logic by the synthesis tool. Hence the computation will be finished in one clock cycle.
Division in velog will throw a synthesis-error, "divisor should be an integral multple of 2".
We have to use other way for modeling this.
I was working with only powers of 2, and hence wrote case statements. Please let me know if there is abetter way of doing it.
Regards
"enjoy your work"