Re: saturation
I consulted many books and reached to the following conclusion:
In npn transistor,
‘Saturation region’ is when both the base-emitter (BE) and the base-collector (BC) junction is forward biased.
It occurs only when
V(BE)=0.7 and V(BC) >0 and V(CE) < 0.7
According to the following equations:
V(BC) = V(BE)- V(CE)
As V(BE) =0.7V;
V(BC) = 0.7- V(CE)
So, by the above equation,V(BC) is positive (forward-biased) only when V(CE) is less than 0.7V.
And ‘Saturation point”, V(CE)sat, is that minimum point where DC load line cuts the collector characteristic curve, and at that point maximum Ic(sat) flows, ideally this point should be at V(CE)=0V, but due to thermally generated electrons it is between 0.1V and 0.3V.
So, V(CE) can not go below V(CE)sat, and in some book they also give saturation region ‘a region below V(CE)sat’, i.e between 0<V(CE)<0.3, accordingly this okay as V(CE) b/w 0 to 0.3 : V(BC)>0, and V(CE)<0.7.