what is RTL in ASIC/FPGA/VLSI

[sunidrak]

hi
I want to know abt RTL coding ...! Would any1 plz explain what is RTL coding ? And how it is different from HDL coding
thanks in advance

 

[mkrtich.nazaryan]

RTL is opening like Register Transfer Level. this is HDL code which possible to synthesis. There is also behavior level HDL codes.
https://en.wikipedia.org/wiki/Register-transfer_level

 

[sunidrak]

oh thanks ...
Will u plz explain even more ..! Will u tell RTL for D-Flipflop ....! I don't have much knowledge ..my question might seems freaky for u ...plz explain ....what i understood is ...RTL code is outcome of HDL

 

[mkrtich.nazaryan]

RTL code is same as HDL code which have been written to synthesis not for testing. For example you can use Leonardo Spectrum or Design Compiler tool to synthesis logic cells from RTL HDL codes. Behavioral Level can be used for example for testing branch.

---------- Post added at 15:38 ---------- Previous post was at 15:35 ----------

Just follow to this link https://www.asic-world.com/verilog/intro1.html#Register-Transfer_Level

 

[sunidrak]

oh thanks a lot
and my last question ...What is verification in vlsi ...? In what way its verified ..?

 

[mkrtich.nazaryan]

Verification is really very big topic. For ASIC or VLSI when you starting your design with CMOS structure or BISCMOS or only bipolar, you need to check your final product before sending it to FAB(semiconductor fabrication plant like TSMC). There are some tools (Calibre, Hercules) they can check for example LVS (Layout versus Schematic) or DRC (Design rule Checker) or DFM (Design for Manufacturing) or electromigration inside of your desing. these kind of tools checking is your final product, correct or not. Say in simple words, Verification will give you answer is it possible to make physical device according to your design or not

 

[sunidrak]

thank u so much sir

 

[vs.rishi]

rtl coding is not out come of hdl.rtl is a higher level of abstraction in the design flow.u will have to arrive at different black boxes connected to each other(block diagram) such that the over all circuit will meet the functional requirement.all this is paper work.

Once you achived this u will use different hdls to make your tool understand and when you synthesizethe code you will get a netlist which is often reffered as rtl.so this not an output of tool.

 

[zengqinghe]

good explanation!