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What is metastability and how to recover from it?

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Harinadhan

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hai,
can any body answer my doubts...
1.what is metastability,when does it happen and how to recover from m.s.
2.How synchronisation is done between two clock domains for different signals.

please help me.......................
 

cydi

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metastability

Metastability is the state where your logic behave irrationally. Sometime you get what you want, sometime you dont. Typically happens in the case of two signals changing at the same time. Watch out for the situation.
To sync two clock domains, you will have to sync the slower one with the faster one. i.e "sample" the slower on with faster (using a D-FF or so). alternately, you can use a faster third clock to bring the two into one common domain.
 

Iouri

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metastability

simple way to avoid MS is to run data signal from domain A to domain B is to have atleast two flip flops clocking fro clock B

use search that topic alredy had been disscuss few times
 

dinaganesh

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Re: metastability

metastablilty is an intermediate condition arises due to slope in the practical clock pulse !!

its like stage in between 0' and 1' . this can be eliminated by going to series of flip flops so that the set up time of the first flip flop should be double time of the hold time of the second one . series of flip flops connected which will satisfy this condition will reduce metastability!!
 

sachingorkhe

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metastability

MS is basically due to timing violations i.e. set up and hold time. Its a intermediate state of logic.

For slow clock domain, you can sample slow signal with high clock domain. But it is difficult to sample high speed signal with slow clock. So use 2 level of signal registers to sync the signal. You can also use the fast clock to register the fast signal in a slow domain.
 

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