What is meant by structured ASIC and mask programmable cells

[viswa]

Structured ASIC

what is maent by structured ASIC and mask programmable cells in structured ASIC?If it stands between fpga and asic wat is its similarity to fpga and asic?

 

[arunragavan]

Re: Structured ASIC

Structured ASICs are those which are similar to Cell based ASICs.. take a look at this

h**p://www.synplicity.com/products/structuredasic/

similarity cud be arrangement of the cells.. but seriously ASICs and FPGAs are entirely different.

with regards,

 

[dddain_bramage]

Re: Structured ASIC

> what is maent by structured ASIC and mask programmable cells in structured ASIC?

Structured ASICs are often compared to "standard-cell" ASICs. In standard-cell ASICs, the customer has complete freedom to implement all "layers" of wafer (logic, interconnect, via, etc.) In a structured ASIC, the manufacturer sells a "standardized frame" with circuits already imprinted on the base-layer. It's sort of like an FPGA, where the die-area is populated with a high mixture of logic gates (AND, OR, NOT, adders, etc.), and some amount of more advanced resources (RAM, register files, PLLs, I/O blocks.)

Compared to standard-cell ASICs, structured-ASICs (of the same die-area) have lower utilization (i.e. lower logic capacity), but faster turnaround time (from tapeout to first silicon) and lower NRE costs. The faster turnaround time is not because structured-ASICs are fabricated faster -- it's because the structured-ASIC product has a 'standardized' base-layer. For the manufacturer's product-line, all chips of the product line are identical, so the mfg can fabricate them before a customer submits an order. This allows faster delivery of first silicon, since the customer's turnaround time is merely the metal-layer finalization (upper interconnect layers) of the ASIC. Likewise, each customer's ASIC-order only requires a partial set of masks (the upper layers), reducing the NRE-cost for a tapeout.

Standard-cell ASICs generally have a lower "per-unit" cost. And obviously, since standar-cell ASICs start with a 'blank floorplan', the customer has complete freedom to customize the die for his application. (Limited only by talent and process design rules.) But as foundry processes continue to shrink, standard-cell tapeouts continue to skyrocket. The breakeven point for a profitable standard-cell ASIC product continues to move higher and higher (in terms of volume.) So structured ASICs and FPGAs will likely fill mid-volume applications.

Like standard-cell ASICs, structured ASICs are offered in different product lines. There are products with just 1 customer interconnect layer (only 1 orderable mask-layer), and there are products with 4-5 interconnect layers (4-5 orderable mask-layers.) And of course, they product differentiation includes "pre-embedded IP" (memory controller, microcontroller, high-speed I/O, embedded RAM/ROM, etc.)