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I will tell u simply what it is :
say u have a very big combinational circuit .. that requires like 5 seconds to process its inputs and thru the results at the output .. (5 seconds is too big .. but just for the demo of the idea) ..
and u want to have ur design fast .. like to operate it with a speed clock .. then .. if this is the case, u will experience a very big delay between the input and the output of ur combinational circuit .. and this will prohibt u from using a fast clock. ..
the solution to this is pipelining .. which is .. to divide ur combinational circuit into 2 consequetive circuits .. the first one say completes its procession in 2.5 seconds .. and the second one also in 2.5 seconds .. and put a flip flop in between the 2 circuits ..
hence u will get ur work done in 2 clock cycles instead of one .. but u will keep ur system running at very high speed clock ..
There is some similarity with manufacturing a product, let's say a car. For simplicity we consider a serial assemply line.
It takes 2 units two assemble the carbody.
It takes another 2 units of time to assemble the wheels.
Another 2 units to assemble the chairs.
Another 2 units to assemble the engine.
Another 2 units two assemble the carbody.
So in total it takes 12 units of time to produce the car.
In case of an assembly line no one is waiting for onather. So while you are assemling the carbody , the other unit is assembling the wheels to a carbody assembled previously. There is no miracle of course, because even in that case the time need to complete a cra is 12 units of time.
However, after starting up the production (12 units passed), the throughput will be increased, thus, you will complete a car at every 2nd time unit.
The same is true in cae of uP. Every instruction needs several lower task to be completed (fetch data from memory, do some operation on it, and write back to memory). The first uP do that in the way, that an instruction was started only after the prevoius one was completed. In case of pipeline that is not true anymore, the instruction executions are overlapped in the way as the car assemply line, that is, the lower task belonging to an instruction are executed in serial, but differnet taks belonging to different instructions are executed in parallel.
Pipelining is an implementation technique in which multiple instructions are overlapped in execution. An unpipelined processor must complete the execution of each instruction before it begins the execution of the next. A pipelined processor consumes less time compared to a non-pipelined processor.