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It is an advanced lithographic node used in volume CMOS semiconductor fabrication. Transistor gate lengths can reach as low as 25 nm on a nominally 65 nm process.
The devices were scaled as the processes reach lower values. A 65nm silicon technology roughly doubles transistor density compared to the previous 90nm generation.
A transistor is generally charectarised by its gate length (L) & gate width (W). Gate length is the distance, an electron has to travel from highly doped Source to Drain. Xnm refers to the gate length.
apprxoximately each lower node technology is "0.7 times the previous technology"
i.e 130 nm, 90 nm, 65 nm and 45 nm