What is input delay and output delay?

[nemolee]

What is input delay and output delay?
How do I estimate these values?

 

[no_mad]

if you are looking for set_input_delay & set_output_delay, then here is the answer:

set_input_delay is sets input path delays

Added after 8 minutes:

if you are looking for set_input_delay & set_output_delay, then here is the answer:

set_input_delay is sets input path delays on input ports relative to a clock edge.

meaning, if you have
clock period = 10
input delay = 3

Thus, your data will be arrived after 3.

Same thing happen when you set "set_output_delay"

#You can check this in Design Compiler user guide or you can read any synthesis books.

Hope it helps

 

[claint]

Yes,you should search in sold , you will be clear after reading dc related documents.

 

[jjww110]

please refer to sold,very clear

 

[rajavel]

Input Delay is the delay inherited by the signal coming at the input of a Gate. It depeds on the capacitance value at the gate pin. This can be characterised in Hspice.(More details refer to Hspice Manual).

Output Delay is the combination of delay of gate ( internal delay) + delay due to load connected at the output of the gate. It is calculated as 50% of input vtg 50% of output vtg

 

[silencer3]

i suggest to apply input & output delays on the PORT's rather inside. Use DC to time budget your design based on toplevel I/O delays and do the bottom-up synthesys.

search the SOLD for precise def on input and output delays. above post gives basic def. but u have to specify both min&max input & output delays for DC and PT

 

[beckchm]

It is very important for the synthesis.

You must set the input delay and output delay to describe the external environment for IO ports .

 

[anjali]

input / output delays are specified on input / output ports,
if the arrival / departure times of signals on input / output ports is not exactly at the active edge of the clk.

generally these r used to model the environment.

 

[vid31]

Hi,

Can you tell me what is SOLD?

Thanks,
Vidyut

i suggest to apply input & output delays on the PORT's rather inside. Use DC to time budget your design based on toplevel I/O delays and do the bottom-up synthesys.

search the SOLD for precise def on input and output delays. above post gives basic def. but u have to specify both min&max input & output delays for DC and PT

 

[alam4vlsi]

Hi Vidyut,

SOLD is Synopsys Documentation on the Web is a collection of online manuals that provide instant access to the latest support information. With this program, customers can be sure that they have the latest information about Synopsys products.



Thanks,

Alam

 

[whenkey]

every core is designed with Flip Flops and combinational cells. So, while doing synthesis we have to tell the tool regarding our design constraints.

The main constraint is create_clock. With this command we are applying clock period to our design.

Every design is having four type of paths:
1. FF to FF path.
2. Input port to FF path.
3. FF to output Path.
4. Input to output path (direct combinational path from input to output).

we have to give the constraints to all these paths. If we specify clock frequency then all the FF to FF paths are constrained. Why because entire operation between FF to FF should be complete in one clock period. (So 1st path is done).

suppose in top design 4 sub blocks are there. You are currently synthesizing one of those block. Assume all the blocks are running at same clock frequency. For design under analysis some input to FF (or FF to Output) path is there which contains some combinational logic. If you see design from top level this path is also a FF to FF path. But some part is in another block and remaining part is in current design. So from clock period how much time is needed for logic present in outside block is called input delay. similarly output delay also mentioned. while synthesizing the design for these boundaries, the tool will subtract the input delay from clock period and then with remaining period the logic is optimized. (2nd and 3rd paths are done).

set_max_delay is used to constraint the 4th path. (we can also use input_delay and output_delay commands w.r.t virtual clock for constraint this path) (4th is also Done)