When clk is high, the change of D should not affect the output Q, but in my circuit, Q changes with D. I am using bsim-cmg model. Here is the netlist and wave8-O.
When clk is high, the change of D should not affect the output Q, but in my circuit, Q changes with D. I am using bsim-cmg model. Here is the netlist and wave8-O.View attachment 149503View attachment 149504