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Glitch suppression with regard to what circuit? A glitch is a narrow unwanted signal transition. Glitch suppression, of course, is trying to eliminate these unwanted pulses.
One place this occurs is when a multiplexer is used to switch between two clock sources. If the clocks are not syncronized, then glitches in the clock output can occur when switching between clocks. This is due to the fact that you can only sync with mux control signal to one of the clocks therefore, glitches are possible when switching to the other clock. FPGAs are now adding special circuitry to the clock muxes to eliminate these glitches. The mux basically holds its state until the next clock transition, it switches on edges rather than levels.
one of the most widely used trick to supress glitch in the design is to use flip-flop instead of latch. I pressume that u understand the difference between latch and f/f.
In asic terminology .. cross talk between aggressor net and victim net causes Glitch and some delay is also induced
hence to avoid glitch ..double spacing is maintained for clock net
Shiv
Actually glitch results in wastage of power due to transition of low to high or high to low state. This unwanted transition occurs because we are not receiving the input signals at the gate at the same time and which results in transtion of state of te output and which is corrected when second signal arrives and we have again transtion of state and more loss of power.
glitch supression can be down by making balanced connections such that both input signals arrive at the same time.
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