[SOLVED] What is Functional gate-level simulation?

[irun2]

This question seems to be stupid but I really need clarification. My understanding is that we can use EDA tool such as Verilog-XL to do gate-level simulation with the post-layout, or the netlist that after DC synthesis.
But my colleague told me that's not gate-level simulation, I have to do the simulation using AMS, (use the netlist to generate a symbol then setup a circuit schematic for simulation) like the Transient analysis.

 

[ljxpjpjljx]

if your do digital design ,you are right!

 

[irun2]

if your do digital design ,you are right!

Yes, I am refering to digital design!
But what if it refers to mixed signal design?

 

[jbeniston]

As a digital designer, a gate level sim is usually a logic gate simulation. i.e. simulation of post-synthesis / p&r netlist.

If an analog designer is talking about a gate level sim, he's probably talking about a transistor level sim.

 

[phoenixfeng]

You are right, trust yourself