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what is floorplan guideline and how can i say it is goodfl

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vamsi_addagada

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what is floorplan guideline and how can i find it is good floorplan please replay
 

Re: what is floorplan guideline and how can i say it is go

Floorplanning can never be judged without visual inspection. It a visual art.
If I were to loosely characterize , if you can utilize your floorplan area well enough ( lets say 80% if tool can handle ) and minimize the amount of routing layers/resources used without any congestion/timing/IR issues , you have a decent floorplan "to start with"

vamsi_addagada said:
what is floorplan guideline and how can i find it is good floorplan please replay
 

HI,

As I am new to PD, Can you please help me where i can get the documentation of performing ASIC floorplan, Like Placement of Macro's, Legalize, Net placement of the Macro's, Various types of floorplan, Placement of straps etc...

None of CMOS design book that i read is giving me this information as Why should i Keep the macro as near to the IO's and why analog macros to be placed next to IO's.

After trail and error method when i found the perfect way, project manager would say other wise that this way is already defined and why did i took long time to do this.

Plz help me with wat all procedures and things i need to know before starting the FP.

Thanks And Regards
Lohi
 

Re: what is floorplan guideline and how can i say it is go

First understand how the data is flowing by going through the design architecture document or request your RTL integration engineer/IP owner to provide one. Once you have the diagram with you. You can place the hard macro's according to logical hierarchy based on the data flow without violating the guidelines.
 

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