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1) This is the path that physically present but are not logic path.
2) They are asynchronous path and can be valid at any moment of time.
3) They lead to lot of timing issue.
4) If false path are not configured during synthesis, the synthesis tool may try to optimize this path
5) No timing issues ------Example Reset signal,
Occurrence 1) If clk to Reset and set signals are not analyzed 2) Global clk to clk if analyzed 3) Clk to clk if not analyzed.