what is data preparation in physical design?

[vamsi_addagada]

cell footprint + physical design

plz any one explain what is data preparation in physical design?

 

[raju3295]

What ever i feel related to Data preparation in the PD is preparing the noise analysis libs (CDBs in cadence world ) ,the foundary data, the required lef and timing libs ...etc.. i work in cadence world so i got these things, and will be different in other EDA tools like synopsys or magma

 

[vlsitechnology]

When you start a new project, you first have to determine whether the
FP/IP design data is valid and consistent. Unless the data has already been checked and validated, you should assume that there are Pre-CTS
inconsistencies and other problems that must be resolved before CTS proceeding.


Data preparation involves Validating the netlist and libraries,checking timing constraints Syntax,Validating Timing constraints, Resolving Footprint Inconsistencies,Validating floorplan,Generating Cap Table for RC extraction and for calculating the delay...

Hope u got the idea...If u still hv any doubts then u can ask me...

Reply me

 

[raju3295]

Excellent vlsi ,, hope you are very much expierienced in this industry

 

[sowmya005]

Hi VLSItechnology,
would u pl elaborate on how u resolve the footprint inconsistencies?

thanks,
Sowmya

 

[raju3295]

foot prints are generally used while optimizing ,upsizing or downsizing,, so tool will replace any cell with similar foot print,
if two std cells which have same foot print, they should be logically same i,e functionality and no of i.os, then tool can use them for optimizations,
if footprint is inconsistent, then the optimizations may result in invalid data