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In a big design including flops, if there is too much delay due to combinational circuits between two particular flops, the clock time period should be as high as that.. but the trade off cannot be afforded just for a single combinational ckt. in a big design.. So the solution is by using a latch.. when a latch is used instead of the flop after the long delay, the clock period can be considerably reduced and the latch gets its data some time after the positive edge of the clock.. This is a great boon for developing microprocessors with low clock frequencies..
Note: The delay of the combinational circuit must be less, so that the data from the latch reaches the next flop before the clock..
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cycle stealing occurs when combinational logic is moved from one clock phase to another in order to equalise latch-to-latch signal delays throughout a latch based design having multiple latch-to-latch stages.Synthesis tools may have the ability to automatically perform cycle stealing during optimization.