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What is ATPG and why is it needed?

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pravi

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what is ATPG and why it is needed?
what are the inputs to a ATPG tool and output of a ATPG tool?
How we can differentiate ATPG and Testbench
 

tarkyss

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ATPG

ATPG is Auto Test Pattern Generate, it is for test,
while testbench is for verification,
test is to check manufacture error
verification is to check design error
 

dr_dft

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Re: ATPG

pravi said:
what is ATPG and why it is needed?
what are the inputs to a ATPG tool and output of a ATPG tool?
How we can differentiate ATPG and Testbench

ATPG stand for Automatic Test Pattern Generation. It takes a gate level netlist, along with some input and output constraints, clock definitions, scan chain definitions, and generates a test pattern that can be used to find manufacturing defects in the real silicon. It also produces a fault coverage report that tells you how good your test it, and which nets are and are not covered by the test pattern.

A testbench is basically a simulation model used to simulate a design. The design can be a block, or the full chip, and the model can be behavioral, rtl, or gate. A testbench can be used for many reasons. The most common usage is a verification testbench, used to verify the correctness of the functionality of the design before taping out a chip.
A verification testbench will normally include a model of the block or chip under test, other modules or chips that drive stimulus to the chip under test, and some checker module to indicate whether the outputs behave according to specification.
You can also have a testbench that verifies the pattern produces by the ATPG tool. This testbench will normally mimic how a semiconductor tester (ATE) will sequence the test pattern into the chip under test, and check whether the outputs of the chip is identical to the expected values in the test pattern.
 

pravi

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Re: ATPG

how the pin limitation is in ATPG tool.i mean to ask what do we mean by saying number of pins in ATPG.
 

dr_dft

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ATPG

Pravi,
I think you misunderstood me. I meant by input and output constraints is defining some inputs to certain logic value to enable ATPG to run correctly. For example, scan enable or and test mode signals.
The number of pins usually does not matter in ATPG, but it does matter on the ATE. But that is different issue :)
 

pravi

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Re: ATPG

can u just tell me any ATPG tool and how we are generating test vectors .any formula is there
 

dr_dft

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Re: ATPG

The most popular commercial ATPG tools are TetraMax from Synopsys and Fastscan from Mentor Graphics. There are other ATPG tools like Encounter Test from Cadence and TurboScan from Syntest.
Go to www.design-for-test.com/dft_links.html to find links to these tools.

Most people don't bother about understanding the algorithm used to generate these patterns (unless your are writing an ATPG tool), as long as the ATPG tool produces a good test pattern.
However, if you are interested, you follow the Academic Research links in the above-mentioned website. There you can find all you want to know about ATPG and more.
 
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