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In my opinion, it check against errors during layouting, such as a P substrate guardring inadvertently connected to VDD and Nwell guardring connected to gnd.
If these errors exist and you didn't run ERC, calibre will issue a warning about soft connection conflict during LVS anyway.
Yes in ERC (Electrical Rule Checks) there are certain checks like
1) Any Floating Nwells .
2) Any Floating Substrates.
2) Is Nwell tap connected to GND
3) Is PSubstrate tap connected to VDD
4) Any transistor is connected between VDD and GND
These Checks are very important to know, must inform to designer or team lead to identify for any drastic errors which may cause circuit malfunction or circuit distruction.
The ERC checks are mentioned above.
Extraction checks means : During LVS there are few steps like device recognisation, connectivity extraction and comparition. During "connectivity extraction" if the tools founds any errors it will give "Extraction errors" . The connectivity errors are like
1) Different Ports are shorted (like VDD and VSS are shor).
2) Same Port name in different nets.
3) Same net have different Port names.
If the Extraction error occurs during lvs , the layout and schematic comparison process will not takes place and tool abort with Extraction errors.
I think this information helps u..