Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what is a transparent latch?

Status
Not open for further replies.

bradyue

Member level 2
Joined
Jan 18, 2008
Messages
47
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,603
is there any diffs between transparent latch and D-latch?
 

yes transparent latch and D-Latch is Same
 

Hi,

Test compiler replaces latches with scannable latches wherever possible. If TC can't find scan cell equivalents for the latches, it marks the latches as non scan and issues warnings.

You can instruct TC to treat a non-scan latch as as a transparent latch using set_scan command.

In transparent mode, the values at the output pins of a latch depend only on the current values at the inputs, not on the stored value. A simple D-latch is in transparent mode when the enable pin is active.

D G Qactual Qtest compiler
0 1 0 0
1 1 1 1
x 0 Qprev x

Regards,
CSuresh
 

REPLY

Hi,
Whenever Enable signal is 1, You will get the same input as the output. THatsy we are referring latch as a transparent latch.

Regards,
siva
vlsiva@yahoo.co.in
 

yes both are same. Latch is said to be transaparent as it gives the same output as the input as long as there is enable to the latch is high.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top