What is a state machine and how to implement it in Verilog?

[sameem_shabbir]

Hi all
I have two questions to ask

1. What is a state machine?
2.How to implement it in verilog

Thnx

 

[kvingle]

Re: State machine

to know what a state machine is...
refer any basic digital electronics book..
or their is a web site that might help you
https://www.google.com
and if you want to learn how to code a state machine in verilog...
refer to any basic book on verilog..such as sameer palnitkar's primer
regards..

 

[deepu_s_s]

State machine

there are mainly two kind of state machines

Mealy FSM
Moore FSM

in the first kind, the outputs depends on the present state and the inputs.

in the second kind, the output depends only on the present state.

For coding in verilog refer to any verilog design books. you can fing plenty of books in the form

Thanks and regards
Deepak

 

[soloktanjung]

Re: State machine

hi sameem,

i also learn verilog at the moment. this link will help u about FSM using verilog. hope this help.

https://www.asic-world.com/verilog/memory_fsm2.html#Introduction_to_FSM

regards,

 

[calm]

State machine

Mealy FSM
Moore FSM

 

[anandanips]

Re: State machine

there are two state machines.
1.melay state machine(melay FSM)
2. moore state machine(moore FSM)



verilog code for this is thereb in digital design(3rd edition) by morris mano book.you can refer it.