What is a power mosfet?

[jgkoh78]

vdmos layout

im working on a assig in designing a mixer with n type mosfet. There is alot of different mosfet. What is a suitable mosfet for this circuit? Is power mosfet the same as normal mosfet?

 

[m.salehi]

high voltage power lateral mosfet

hi,
the parameters of mosfet that used in Mixer performance are needed.
please refer to mixer parameters that u need then u can select the best mosfet for ur choice, for example noise, isolation, ....
eegards.

 

[jgkoh78]

fairchild rench mosfet process

What would be the suitale mosfet for the below? IS the freeware spice able to do the below requirments?

IEEE 802.11a/b/g WLAN standards use a mixer circuit that has the following frequency parameters: RF input frequency: 2.4 GHZ LO (Local Oscillator) frequency: 2.5 GHz IF Frequency: 100 MHz.

The design goals are a reasonable gain (G > 5dB), sufficiently linear (IP3 >-10 dBm) and low power dissipation (Pdiss <50 mW). Include the following plots in your report: &#56256;&#56473; Conversion gain (frequency domain, AC analysis). &#56256;&#56473; Linearity elements: 1 dB comparison and IP3 (frequency domain, AC analysis). &#56256;&#56473; Time domain and FFT domain plots showing the mixer functions correctly (Transit analysis). &#56256;&#56473; Power consumption plot

 

[Euler's Identity]

power mosfet parasitic inductance

"sufficiently linear"

I'm no engineer but...

Power MOSFETs often have a built-in drain to source diode, as they often are designed to be switching high current loads...

diodes are non-linear...

mixers are non-linear, as you want the distortion that creates the sum and difference frequencies...

I started EE school, finished EET, but decided to stop going to EE because it wasn't fun.


At this stage of the game, why don't you know what characteristics you want in a MOSFET for your mixer? Doesn't your instructor give you any clues? You're learning to engineer electric circuits and systems. Your instructor is supposed to be helping you learn. Your instructor is supposed to know and then, with that knowledge, give you clues toward discovering that knowledge for yourself via your studies. Where are your clues? Have you been taught how a mixer works? What kind of power output do you want, for example? What input current will you need for that power output? You mentioned frequencies. How fast will your MOSFET choice need to switch? What about mating your mixer to the outside world? What impedance is out there? Will you have a stable circuit or will it be prone to undesirable oscillation unless certain conditions are true?

Also, find some MOSFET manufacturers (ST, Zetex, Fairchild, IR etc) and study their application notes. Search their knowledge bases for "mixer" and "fet." (They, alot of them, have SPICE models too, and, you can add models, a few, to student PSpice, or modify...)

...but bear in mind, I'm no engineer, just a tech. Engineers reading this could be laughing themselves silly over what I've said. I'm very much an SOP engineer (seat o' pants).

 

[mmike]

site:edaboard.com safe operating area

A Power MOSFET is a specific type of Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) designed to handle large powers. Compared to the other power semiconductor devices (IGBT, Thyristor...), its main advantages are high commutation speed and good efficiency at low voltages. It shares with the IGBT an isolated gate that makes it easy to drive.

It was made possible by the evolution of the CMOS technology, developed for manufacturing Integrated circuits in the late 1970s. The power MOSFET share its operating principle with its low-power counterpart, the lateral MOSFET.

The power MOSFET is the most widely used low-voltage (i.e less than 200 V) switch. It can be found in most power supplies, DC to DC converters, low voltage motor controllers.
Contents
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* 1 Basic structure
* 2 Blocking voltage
* 3 On-state characteristics
o 3.1 On-state resistance
o 3.2 Breakdown voltage/on-state resistance trade-off
o 3.3 Body diode
* 4 Switching Operation
o 4.1 Capacitances
+ 4.1.1 Gate to source capacitance
+ 4.1.2 Gate to drain capacitance
+ 4.1.3 Drain to source capacitance
o 4.2 Other dynamic elements
+ 4.2.1 Packaging inductances
* 5 Limits of operation
o 5.1 Gate oxide breakdown
o 5.2 Safe operating area
+ 5.2.1 Drain to source resistance
+ 5.2.2 Maximum drain to source voltage
+ 5.2.3 Maximum drain current
+ 5.2.4 Maximum temperature
* 6 Technology
o 6.1 Layout
+ 6.1.1 Cellular structure
o 6.2 Structures
+ 6.2.1 P-substrate power MOSFET
+ 6.2.2 VMOS
+ 6.2.3 UMOS
+ 6.2.4 CoolMOS
* 7 See also
* 8 Notes
* 9 References

[edit]

Basic structure
Fig. 1: Cross section of a VDMOS, showing an elementary cell. Note that a cell is very small (some micrometres to some tens of micrometres wide), and that a power MOSFET is constituted of several thousand of them.
Enlarge
Fig. 1: Cross section of a VDMOS, showing an elementary cell. Note that a cell is very small (some micrometres to some tens of micrometres wide), and that a power MOSFET is constituted of several thousand of them.

Several structures have been explored at the beginning of the 1980s, when the first Power MOSFET were introduced. However, most of them have been abandoned (at least until recently) in favour of the Vertical Diffused MOS (VDMOS) structure (also called Double-Diffused MOS or simply DMOS).

The cross section of a VDMOS (see figure 1) shows the "verticality" of the device: It can be seen that the source electrode is placed over the drain, resulting in a current flow mainly vertical when the transistor is in the on-state. The "diffusion" in VDMOS refers to the manufacturing process: the P wells (see figure 1) are obtained by a diffusion process (actually a double diffusion process to get the P and P+ regions, hence the name double diffused).

Power MOSFETs have a different structure than the lateral MOSFET: as with all power devices, their structure is vertical and not planar. In a planar structure, the current and breakdown voltage ratings are both function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With a vertical structure, the voltage rating of the transistor is a function of the doping and thickness of the N epitaxial layer (see cross section), while the current rating is a function of the chanel width. This makes possible for the transistor to sustain both high blocking voltage and high current within a compact piece of silicon.

It is worth noting that power MOSFETs with lateral structure exist. They are mainly used in high-end audio amplifiers. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications, so they are only used in On or Off states.
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Blocking voltage
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On-state characteristics
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On-state resistance
Fig.2: Contribution of the different parts of the MOSFET to the on-state resistance.
Enlarge
Fig.2: Contribution of the different parts of the MOSFET to the on-state resistance.

When the power MOSFET is in the on-state (see MOSFET for a discussion on operation modes), it exhibits a resistive behaviour between the drain and source terminals. It can be seen in figure 2 that this resistance (called RDSon for "drain to source resistance in on-state") is the sum of many elementary contributions:

* RS is the source resistance. It represents all resistances between the source terminal of the package to the channel of the MOSFET: resistance of the wire bonds, of the source metallisation, and of the N+ wells;
* Rch. This is the channel resistance. It is directly proportional to the channel width, and for a given die size, to the channel density. The channel resistance is one of the main contributors to the RDSon of low-voltage MOSFETs, and intensive work has been carried out to reduce their cell size in order to increase the channel density;
* Ra is the access resistance. It represents the resistance of the epitaxial zone directly under the gate electrode, where the direction of the current changes from horizontal (in the channel) to vertical (to the drain contact);
* RJFET is the detrimental effect of the cell size reduction mentioned above: the P implantations (see figure 1) form the gates of a parasitic JFET transistor that tend to reduce the width of the current flow;
* Rn is the resistance of the epitaxial layer. As the role of this layer is to sustain the blocking voltage, Rn is directly related to the voltage rating of the device. A high voltage MOSFET requires a thick, low-dopped layer (i.e highly resistive), whereas a low-voltage transistor only requires a thin layer with a higher doping level (i.e less resistive). As a result, Rn is the main responsible for the resistance of high-voltage MOSFETs;
* RD is the equivalent of RS for the drain. It represents the resistance of the transistor substrate (note that the cross section in figure 1 is not at scale, the bottom N+ layer is actually the thickest) and of the package connections.

[edit]

Breakdown voltage/on-state resistance trade-off
Fig. 3: The RDSon of the MOSFETs increase with their Voltage rating.
Enlarge
Fig. 3: The RDSon of the MOSFETs increase with their Voltage rating.

When in the OFF-state, the power MOSFET is equivalent to a PIN diode (constituted by the P + diffusion, the N- epitaxial layer and the N+ substrate). When this highly non-symmetrical structure is reverse-biased, the space-charge region extends principally on the light-dopped side, i.e over the N- layer. This means that this layer has to withstand most of the MOSFET's OFF-state drain-to-source voltage.

However, when the MOSFET is in the ON-state, this N- layer has no function. Furthermore, as it is a lightly-dopped region, its intrinsic resistivity is non-negligible and adds to the MOSFET's ON-state Drain-to-Source Resistance (RDSon) (this is the Rn resistance in figure 2).

Two main parameters govern both the breakdown voltage and the RDSon of the transistor: the doping level and the thickness of the N- epitaxial layer. The thicker the layer and the lower its doping level, the higher the breakdown voltage. On the contrary, the thinner the layer and the higher the doping level, the lower the RDSon (and therefore the lower the conduction losses of the MOSFET). Therefore, it can be seen that there is a trade-off in the design of a MOSFET, between its voltage rating and its ON-state resistance. This is demonstrated by the plot in figure 3.
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Body diode

It can be seen in figure 1 that the source metallization connects both the N+ and P implantations, although the operating principle of the MOSFET only requires the source to be connected to the N+ zone. However, if it were, this would result in a floating P zone between the N-doped source and drain, which is equivalent to a NPN transistor with a non-connected base. Under certain conditions (under high drain current, when the on-state drain to source voltage is in the order of some volts), this parasitic NPN transistor would be triggered, making the MOSFET uncontrollable. The connection of the P implantation to the source metallization shorts the base of the parasitic transistor to its emitter (the source of the MOSFET) and thus prevents spurious latching.

This solution, however, creates a diode between the drain (cathode) and the source (anode) of the MOSFET, making it only able to block current in one direction.
[edit]

Switching Operation
Fig. 4: Location of the intrinsic capacitances of a power MOSFET.
Enlarge
Fig. 4: Location of the intrinsic capacitances of a power MOSFET.

Because of their unipolar nature, the power MOSFET can switch at very high speed. Indeed, there is no need to remove minority carriers as with bipolar devices.

The only intrinsic limitation in commutation speed is due to the internal capacitances of the MOSFET (see figure 4). These capacitances must be charged or discharged when the transistor switches. This can be a relatively slow process because the current that flows through the gate capacitances is limited by the external driver circuit. This circuit will actually dictate the commutation speed of the transistor (assuming the power circuit has sufficiently low inductance).
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Capacitances

In the MOSFETs datasheets, the capacitances are often named Ciss (input capacitance, drain and source terminal shorted), Coss (output capacitance, gate and source shorted), and Crss (reverse capacitance, gate and source shorted). The relationship between these capacitances and thoses described below is:

\begin{matrix} C_{iss} & = & C_{GS}+C_{GD}\\ C_{oss} & = & C_{GD}+C_{DS}\\ C_{rss} & = & C_{GD} \end{matrix}

Where CGS, CGD and CDS are respectively the gate-to-source, gate-to-drain and drain-to-source capacitances (see below). Manufacturers prefer to quote Ciss, Coss and Crss because they can be directly measured on the transistor. However, as CGS, CGD and CDS are closer to the physical meaning, they will be used in the remaining of this article.
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Gate to source capacitance

The CGS capacitance is constituted by the parallel connection of CoxN+, CoxP and Coxm (see figure 4). As the N+ and P regions are highly doped, the two former capacitances can be considered as constant. Coxm is the capacitance between the (polysilicon) gate and the (metal) source electrode, so it is also constant. Therefore, it is common practice to consider CGS as a constant capacitance, i.e its value does not depend on the transistor state.
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Gate to drain capacitance

The CGD capacitance can be seen as the connection in series of two elementary capacitances. The first one is the oxide capacitance (CoxD), constituted by the gate electrode, the silicon dioxide and the top of the N epitaxial layer. It has a constant value. The second capacitance (CCDj) is caused by the extension of the space-charge zone when the MOSFET is in off-state (see the section Blocking Voltage). Therefore, it is dependant upon the drain to source voltage. From this, the value of CGD is:

C_{GD}=\frac{C_{oxD}\times C_{GDj}\left(V_{GD}\right)}{C_{oxD}+ C_{GDj}\left(V_{GD}\right)}

The width of the space-charge region is given by [1]

w_{GDj}=\sqrt{\frac{2\epsilon_{Si}V_{GD}}{qN}}

where εSi is the permittivity of the Silicon, q is the electron charge, and N is the doping level. The value of CGDj can be approximated using the expression of the plane capacitor:

C_{DGj}=A_{GD}\frac{\epsilon_{Si}}{w_{GDj}}

Where AGD is the surface area of the gate-drain overlap. Therefore, it comes:

C_{GDj}\left(V_{GD}\right)=A_{GD}\sqrt{\frac{q\epsilon_{Si}N}{2V_{GD}}}

It can be seen that CGDj (and thus CGD) is a capacitance which value is dependant upon the gate to drain voltage. As this voltage increases, the capacitance decreases. When the MOSFET is in on-state, CGDj is shunted, so the gate to drain capacitance remains equal to CoxD, a constant value.
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Drain to source capacitance

As the source metallization overlaps the P-wells (see figure 1), the drain and source terminals are separated by a P-N junction. Therefore, CDS is the junction capacitance. This is a non-linear capacitance, and its value can be calculated using the same equation as for CGDj.
[edit]

Other dynamic elements
Equivalent circuit of a power MOSFET, including the dynamic elements (capacitors, inductors), the parasitic resistors, the body diode.
Enlarge
Equivalent circuit of a power MOSFET, including the dynamic elements (capacitors, inductors), the parasitic resistors, the body diode.
[edit]

Packaging inductances

To operate, the MOSFET must be connected to the external circuit, most of the time using wire bonding (althoug alternative techniques are investigated). These connection exhibit a parasitic inductance, which is in no way specific to the MOSFET technology, but has important effects because of its high commutation speed. Parasitic inductances tend to maintain their current constant and generate overvoltage during the transistor turn off, resulting in increasing commutation losses.

A parasitic inductance can be associated with each terminal of the MOSFET. They have different effects:

* the gate inductance has little influence (assuming it is lower than some hundreds of nanohenrys), because the current gradients on the gate are relatively slow. In some cases, however, the gate inductance and the input capacitance of the transistor can constitute an oscillator. This must be avoided as it results in very high commutation losses (up to the destruction of the device). On a typical design, parasitic inductances are kept low enough to prevent this phenomenon;
* the drain inductance tends to reduce the drain voltage when the MOSFET turns on, so it reduces turn on losses. However, as it creates an overvoltage during turn-off, in increases turn-off losses;
* the source parasitic inductance has the same behaviour as the drain inductance, plus a feedback effect: at turn-off, the voltage across the source inductance tends to increase the value of VGS, the gate to source voltage, making in turn the transistor turn-on. The same mechanism operates at turn-on and tends to turn-off the MOSFET. The source inductance makes commutation last longer, thus increasing commutation losses.

[edit]

Limits of operation
[edit]

Gate oxide breakdown

The gate oxide is very thin (100 nm or less), so it can only sustain a limited voltage. In the datasheets, manufacturers often state a maximum gate to source voltage, around 20 V, and exceeding this limit can result in destruction of the component. Furthermore, a high gate to source voltage reduces significantly the lifetime of the MOSFET, with little to no advantage on RDSon reduction.
[edit]

Safe operating area

The safe operating area of a power MOSFET is limited by values that can't or shouldn't be exceeded [2]
[edit]

Drain to source resistance

In the on-state, a power MOSFET behaves like a resistor. This obviously means that at a given drain current level, the drain to source voltage is defined by this resistor.
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Maximum drain to source voltage
[edit]

Maximum drain current

At low drain to source voltage, drain current is only limited by power dissipation [3]. However, when High voltage and High current are applied simultaneously (this is often referred to as short circuit conditions), a phenomenon known as second breakdown can occur. It results in triggerring the parasitic NPN transistor (constituted by the N source contact, the P diffusion and the N epi-layer), making the MOSFET uncontrolable.
[edit]

Maximum temperature
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Technology
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Layout
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Cellular structure
This Power MOSFET has a meshed gate, with square cells
Enlarge
This Power MOSFET has a meshed gate, with square cells
The gate layout of this MOSFET is constituted of parallel stripes.
Enlarge
The gate layout of this MOSFET is constituted of parallel stripes.

As told above, the current capability of a power MOSFET is dictated by its channel width. The channel width corresponds to the third dimension of the cross-section visible below

For the sake of cost and size, it is important to keep the transistor die surface as low as possible. Therefore, optimizations to increase the width of channel by surface area (i.e increase the "channel density") have been developed. They mainly consist in creating cellular structures repeated over the whole area of the MOSFET die. Several shapes have been proposed for these cells, the most famous being the International Rectifier's "Hexfet" (hexagonal shape).

An other way to increase the channel density is to reduce the pitch of the elementary structure. This allows for more cells by surface area, and therefore more channel width. However, as the cell size shrinks, it becomes more difficult to ensure proper contact of every cell. To overcome this, a "strip" structure is often used (see figure). It is less efficient than a cell structure of equivalent resolution in terms of channel density, but can cope with smaller pitch.
[edit]

Structures
[edit]

P-substrate power MOSFET

A P-substrate MOSFET (often referred to as PMOS) is a MOSFET with opposite doping types (N instead of P and P instead of N in the cross-section in figure 1). This MOSFET is made using a P-type substrate, with a P- epitaxy. As the channel sits in a N-region, this transistor is turned on by a negative gate to source voltage. This makes it desirable in a buck converter, where one of the terminals of the switch is connected to the high side of the input voltage: with a N-MOSFET, this configuration requires to apply to the gate a voltage equal to Vin + VGS, whereas no voltage over Vin is required with a P-MOSFET.

The main disadvantage of this type of MOSFET is the poor on-state performance: it uses holes as charge carriers, which have a much lower mobility than electrons. As resistivity is directly related to mobility, a given PMOS will have a RDSon three times higher than a N-MOSFET with the same dimensions.
[edit]

VMOS

This structure was used for the first commercial devices [4].
[edit]

UMOS
The UMOS has a trench gate. It is intended to increase the channel density by making the channel vertical
Enlarge
The UMOS has a trench gate. It is intended to increase the channel density by making the channel vertical

In this Power MOSFET structure, the gate electrode is burried in a trench etched in the silicon. This results in a vertical channel. The main interest of the structure is the absence of the JFET effect. The name of the structure comes from the U-shape of the trench.
[edit]

CoolMOS

Especially for voltages beyond 500V some manufacturers, most notably Infineon Technologies, have begun to use a charge compensation principle. Thus the resistance in the epitaxial layer as biggest contributor in high voltage MOSFETs can be reduced by a factor >5.

 

[alitavakol]

power mosfet inductance

power mosfets have approximately thesame characteristics as ordinary (small signal) mosfets but they have one big difference with ordinary small signal mosfets,and that's
their power handling capability.power mosfets can handel lot's of current in their on state and lots of reverse voltage on their off state so their commonly used in power electronic circuits.the ones normally used are by international rectifier namely IRF620
.if you want to make a small signal mixer use the small signal mosfets made by motorola(now freescale)

 

[my_books]

p implantations in power mosfet

Power MOSFET Basics