what is a port in Cadence schematic?

[karaisan]

The left port is a source, resistance is 50ohm, source type is sine, frequenc is 5GHz, amplitude is 100mv, other parameter is blank.
The right is a load, resistance is 500ohm, other parameter is blank.



in SP simulation, S11 is 0.818, it is so calculated, s11=(500-50)/(500+50)=0.818.
s11 equals vlotage reflection coefficient, means v(port14/port15)=100*(1-0.818)=18.2mv.
but in pss simulation, v(port14/port15)=181.8mv, so calculated, 500/(500+50)*100*2=181.8MV.
so act as a voltage divider, but why 100*2 mv?

if i insert a 2-port network between ports, result is same.
R15=100ohm, R14=1kohm, then s11=0.793, but v(R15)=179.3mv(calculated by 100mv*2 and voltage division).
if i change resistance of port15 to standard 50ohm, v(R15) is still calculated by 100mv*2 and voltage division.

it seems port is not simply a voltage source with a source resistance, then what is exactly a port in cadence schematic?
why shoule double amplitude of port before voltage division?
why s11 theory seems not work?
Thanks!

 

[dick_freebird]

I think you need to represent the 50-ohm system properly,
this transmission-line behavior is a key part of s-param
definition and validity.