risc&cisc
Hi,
Well, simply this is no true.
As name says (Reduced Instruction Set Computer) RISC has less instructions ussualy with only one clock cycle .
Whith less instructions you don't need complex instruction decoder, so RISC cores need less transistors (chip area), less power (excelent for mobile units) and higher core speeds than CISCs for same technology.
First RISC architectures were developed for SPACE programs and GaAs technologies (only 40K transistors per chip). For these technologies RISC is only one solution.
Main benefit of RISC architecture is high level language programing.
There is very small defference between programs written in C and programs written in pure assembler.
RISC is low power, high-speed, compiler and programer friendly high level languages oriented architecture.
If you need complex instruction (operation) with RISCs you can synthesize this instructions in software with avaliable RISC instructions.
RISC architectire is not good in all cases especially if your application frequently needs some complex instructions which are not implemented with RISC instruction set.
With CISC architecture you don't always need all complex instruction for some simple tasks. So in most cases you don't use efficient avaliable chip area and waste chip power.
For space and mobile products RISC is only one solution for other products you can use CISC or RISC architectures.