What happens when an input to an FPGA pin is open circuit?

[circuit]

what happens when an input to an fpga pin is open circuit and i see in the code there are buffers to the signal and then shift registers etc ? how is the input to the treated ?

 

[echo47]

fpga pin open

You didn't say which FPGA or how the input is configured. If the input pin is used internally, then the typical FPGA input is very high impedance, so the signal will float. You breathe on it and it will probably change state. It may pick up noise or consume extra power too. Some FPGAs provide configurable pullup or pulldown resistors on input pins.

If the input is unrouted, however, it usually gets an automatic internal weak pulldown or pullup. Consult the data sheet.

 

[circuit]

Re: fpga pin open

Ok lemme explain the situation. I am having an Analog Devices eval board containing xilinx virtex II fpga chip. This board sits like a daughter board on ADC eval board which is sending data/clocks to the fpga chip. The fpga board can be configured with a number of ADC eval boards and hence has some signals which doesnt connect to anything with my current ADC board.

So there is this LVDS signal(terminated using 100ohm resistor) which is being sent to the fpga chip. The ADC eval board doesnt send these signals and hence they are open. When I checked out the code on the fpga chip it had

IBUFDS_LVDS_33 lvds_data_ibufo(.I(A_p), .IB(A_n), .O(A)); as one of statements for buffering the LVDS data. and i see in the UCfile the net has been assigned pin
NET "A_p" LOC = "D1" | IOSTANDARD = LVDS_33 ; Hence I wondered what would happen here.

 

[echo47]

fpga pin open

Ok, Virtex II with floating differential input.
Here's a relevant message from Xilinx answer database (a very helpful resource):
**broken link removed**

 

[circuit]

Re: fpga pin open

thanks ! that is certainly resourceful. Ok there is something else i wanted to ask. we thought of sending two single ended signals to those 2 pins of the fpga chip. hence we removed the resistance between the lvds channels. and thought of reprogramming teh chip incorporating these single ended signals. But then I realised i do not need those signals .

the fpga chip has the orginal program where it expects those two pins to be lvds data and has a lvds buffer on the input and some shift registers. but we have two single ended signals on it.

1) there is data coming through those single ended channels but the code in the fpga chip does not affect how the incoming data is processed (there is a control bit which selects this data when high and in my case its always low, so it doesnt matter what this data is). so is having defined the pins as LVDS and connected them to single ended going to create problem even though it doesnt affect the data/delays.

I know I can redefine the pins to accept lvcmos and new logic levels but wanted to know about this issue....

 

[echo47]

fpga pin open

If you don't exceed the LVDS input voltage spec, then you should be fine.
See Virtex-II Data Sheet section "LVDS DC Specifications (LVDS_33 & LVDS_25)"

Applying nonsense input signals should be harmless because you ignore the LVDS receiver's output.

 

[circuit]

Re: fpga pin open

Aha! thanks. I will redefine the levels as lvcmos33 just to be safe. just a bit of complication, all those DC specifications are with termination resistor of 100 ohm, so with that not being present , what happens to the conditions ?

 

[echo47]

fpga pin open

Not all of them. The outputs say 100 ohms, but not the inputs. Inputs don't care what terminator you install outside the chip.

 

[circuit]

Re: fpga pin open

oh yeah, thanks again ! now this is current situation I am having, one of the pins is open and the other is a 0-2.4V signal. if this is not a problem it will save me a lot of overhead. I know its not right but to do initial testing, it should be ok.

 

[echo47]

fpga pin open

If your design ignores those input pins, and you aren't exceeding their electrical ratings, then no worries.

If you want a more official answer, submit a Xilinx WebCase and wait a day or two. Keep your question short, simple, and clear, or you may get a poor answer.
https://www.xilinx.com/support/clearexpress/websupport.htm

 

[circuit]

Re: fpga pin open

yep thanks a lot ! and can you temme about programming the FPGA chip. there is a xilinx prom with it as well. I understand generation of mcs file from teh bit file and the flash prom is programmed with the bit file. In JTAG/Serial mode, do I add the devices or they are detected automatically and I just right click and program the flash device ?

 

[echo47]

fpga pin open

Sorry, I don't have much experience with those PROMs. Maybe post a new question to this forum.

I normally use a nearby microprocessor to send the Xilinx BIN file (that's a BIT file minus the header) to the FPGA via slave serial or parallel mode. Sometimes I use iMPACT to send my BIT file directly into the FPGA via JTAG.

 

[circuit]

Re: fpga pin open

Okay even while directly sending the bit file to the FPGA chip using the iMPACT tool, say, in JTAG configuration mode, do we have to add the device or it automatically recognizes them as they are powered ? And its just a right click and program ? This is my first time and hence endless list of questions

 

[echo47]

fpga pin open

I'm running iMPACT 7.1 on Win2k. I connect my Parallel Cable IV to my project (such as a Xilinx development board), and then launch iMPACT. It asks a few questions, I select things like "new project", "boundary scan mode", and "automatically connect to cable". Then it auto-detects all the JTAG devices in my project, and displays a diagram of the JTAG chain. I right-click the chip I want to program, click "assign new config file", and tell it the name of my BIT file. Then I right-click it again and select "program".

That's a lot of clicking. I prefer command line tools, so I usually create an iMPACT batch file. Then all I have to do is type "go" and my FPGA gets configured.

If your project contains a JTAG device that iMPACT doesn't recognize (for example an Analog Devices DSP chip), you'll need to find or create a small BSD file that tells iMPACT how to "bypass" that device. I forget exactly how to do that, but it's not difficult.

At some point, the JTAG chain will appear to be backwards. I forget where that occurs, but prepare yourself for that little surprise.

 

[circuit]

Re: fpga pin open

I will try downloading the program..... they dont provide webcase technical support to students