What happens to JKFF after importing to SOC encounter?

[cooldude040]

I have seen a JKFF in verilog netlist before importing a design but after importing a design there is no JKFF why so ??

If there is JKFF in a netlist then it shud be there in our design also right? wt do u say ????

 

[visualart]

SOC encounter

U mey ban the JKFF when the circuit were synthesized.
such as the command of the design compile----set_dont_use JK**

 

[cooldude040]

SOC encounter

If we give that command then the whole functionality gets changed right bcz if there is a connectivity between JKFF and some other component then there might be a problem right?
So y do we remove that JKFF then??......
If the functionality gets changed then it is difficult for the backend designer to design right? So if u remove JKFF then what about the connectivity between JKFF and some other component?
Reply me ........