What exactly is the Verification IP?

[shaikss]

I am new to this verification domain
Some where or the other, I am listening the word Verification IP
I know Internet Protocol(IP)
Whats this Verification IP?
Can u pls elaborate on this
Thanks in advance

 

[kpsai26779]

Verification IP

Hi shaikss

IP stands for Intellectual Property, those are building blocks of systems.

 

[mssajwan]

Verification IP

Hi,
Like other IP's.
These are pre-verified models which can be directly used for verification.
For example USB verification IP is a model against which
u can verify the USB RTL.

Hope it helped.
Manmohan

 

[shobhitk]

Verification IP

Hi VIP means its has a compatibity to attach with any standard protocol such that SATA,USB,AXI etc
and verify you SOC with the Interface , You can Design Your Verification IP in Verilog,VHDL,SystemVerilog , directC , systemC ,
eVC,Vera.......any of them will give you the verification cabability of VIP

 

[phoenixfeng]

Verification IP

VIP is a verified model that used for verification

 

[senddilu]

Re: Verification IP

A verification ip contains some components, which are useful in tesing a design. ( say USB 2.0 or PCIX) .
It contains Stimulus generator that is capable of generating tests (phase level, transfer level etc), coverage collector (to see whether all the tests have been completetly covered), scoreboarder (which checks the expected output with the actual O/P).. like this.
Idea is to automate the test as much as possible and verify the design completely.

 

[dechen]

Verification IP

specman evc

 

[basha_vlsi]

Re: Verification IP

To provide testing block inside the design along with the DUT which is called built-in-self test

while power on the system this checks the entire system

 

[bywater]

Re: Verification IP

I am new to this verification domain
Some where or the other, I am listening the word Verification IP
I know Internet Protocol(IP)
Whats this Verification IP?
Can u pls elaborate on this
Thanks in advance

VIP and IIP are two kinds of IPs.

IIP is used for implementation of design.

VIP is just used to verifiy the design, most of which are IPs too.
VIP could not used to implement design. Verification is its only goal.

 

[niravbhatt]

Re: Verification IP

First of all IP what you know is also right.

But in field of ASIC Design, IP means intellectual Property.

IP can be Design IP. Which is full version of any Design , can be load into FPGA or tapped out for ASIC Chip.

If you you have question for VIP then it is Verification IP.

Verification IP is nothing but the IP only but this IP verifies your DIP (Design IP).

I hope your question is answered.