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jitter is the basically the non-ideal behavior of clock signal. Due to some noise or voltage fluctuations the clock edge may not align edge after edge. This random behavior is called jitter. This should be added to the worst case delay calculations.
well clock jitter is basically a temporal variation in the clock pulse arrival time.. clock skew and jitter are two very important factors which determine the arrival of the global clock pulse with respect to the locally clocked domains!
u can never eliminate the skew. but u can only reduce the clock skew/jitter in a circuit!
I want to add something to arunragavan's answer which i hope can further clarify Skew & Jitter:
Skew: Spatial variation in clock arrival times. It is the variation, when "same" clock edge is seen by two "different" FFs.
Jitter: Temporal variation in clock arrival times. It is the variation, when two "successive" clock edges are seen by the "same" FF.
For example, assume that the clk signal has a freq of 1 MHZ,
In ideal environment each clock edge from outside the world would arrive exactly at the time required one millionth of a secnd after its predecessor,
In the real world, however clk edges may arrive early or late a bit -- this would be the jitter.
The FPGA clock manager can be used to detect and correct this kind of jitter and to provide clean daughter clock signals from the device.
Jitter is “the short-term variations of a signal with respect to its ideal position in time.”
Clock jitter is the variation in timing of a critical instant in a periodic waveform with respect to a jitter free reference.
Might be below link will be useful - https://www.pericom.com/pdf/applications/AB037.pdf
1- turn on and turn off time of transistors are not perfect due to process/voltage/temprature variations. All these variation will cause the same transistor to turn on or off differently each time and that will cause jitter.
2- Noise in general is a main contributor to jitter. noise due to power line varations, transistor switching activities across the die which causes cross-talk and cross talk induces unwanted noise into transistor which in turn effects their normal operation and this translates to clock-to-data jitter.
I see some understood jitter whereas some confused jitter with skew. Haha!
Jitter - A random or temporal variation of clock phase, not arrival time. Main causes of jitter are (1) crosstalks, (2)EMI from largely from power transience and RF signals, (2) internally from common-mode and differential-mode variation. Due to the random characteristic nature of the jitter sources, jitter is random or temporal. PLL can only minimise jitter, at the expense of some drawbacks (which I am not going to tell more).
There are three types of clock jitter: first one is :long-term jitter, the 2nd is : period jitter, the 3rd one is : cycle-to-cycle jitter. all of these three type of jitter are presentation of clcok phase noise. Just like "Distance","Speed",and"Velocity"!
for example. clock to data skew, is the arrival time difference, between the clock signal, and the data signal, from the uP to the memory. you should to control this, in layout design or floorplanning. it shouldn't be too much. there are thresholds.
maybe the memory gets the clock rising edge, and the it thinks, that it can sample the data lines. but the data lines aren't reade in that time moment, because of the skew.
normal clock skew, as i know, is the arrival difference of the same clock signal, to the different memory modules. in synchron systems (sdram) you should to hold this difference between thresholds.
pin skew: some processors doesn't like that they get a far-non-50% clk signal. maybe because of internal pipelining, or multiphase processing.
see memory/processor datasheets, memory bus specifications...
agilent has wery helpful papers about that. and the fairchild's backplane design guide is also helpful.
you should do timing analyses, to inspect them, and should control them in design stage.
these things are depending on noise, pcb line length, earlier databits(isi), unbalanced load of clock lines ...