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What does the TT,SS,FF,FS,SF mean?

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shaq

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ff fs sf ss

Dear all,

Can someone explain TT,SS,FF,FS,FS in detail, respectively?
 

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fs ff ss sf

Actually in real life what we simulate in the simulators we don't get exactly that in the physical design.So as every thing is probabilistic you have to ensure that the chipyou fabricate should work in all process corners. .They are what you have listed.Now suppose you have a speed spec.So if the functionality is achieved in all specs then u have to simulate in Slow-Slow corner to figure out the worst case speed.Similarly for power spec u simulate in FF corner as in that corner the Current is maximum as the transistors have low Vt there.
 

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ff ss corner

Hi,
Fast means operation fastly which reasons from thin gate oxide or other
fabrication variation. vice verse.
best regards
fxxjssc
 

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ss ff tt

TT - Typical NMOS, Typical PMOS
S - slow
F - fast
 

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sf, fs, ff, ss

SS/TT/FF/SF/FS make chip corners, which directly determines your yield
 

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corner ss ff

MOS corner
FF:Fast Fast
SS:Slow Slow
FS:Fast Slow
SF:Slow Fast
 

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corners tt ff ss

Anachip said:
electronrancher said:
as montage said, they stand for typical, slow, and fast. since the transistors vary from lot to lot, we use these process corners to check the effects of process variation on our circuit. if you ask me, the main contributor is tox, which makes both transistor either slow or fast. it's fairly unusual to get sf or fs cases, because this means that something is affecting each type of transistor differently. one way this can happen is if the threshold adjust is too heavy or too light, making the vt of the devices unmatched. but that is pretty minor in my experience, usually the variation affects all devices at once - making them ss or ff..

btw - the combination sf means slow nmos and fast pmos (n is always first).

So, when talking about corner analysis, which one we have to care to most. Is it SS,FF or SF, FS?? Which process the design has to pass the most ? Thanks.

these are mos corners
TT: typical typical
FF:Fast nmos Fast pmos
SS:Slow nmos Slow pmos
FS:Fast nmos Slow pmos
SF:Slow nmos Fast pmos

All the corners have to be taken care for the better yeild.

my finding most of the time SS, 125C, low supply voltage(especially for feedback less ckt) is the most worst corner
 

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circuit design in corners ff, ss, tt

electronrancher said:
You have to care about all of them. When designing your circuit you should know how each transistor has been sized and placed to give a certain operation. If all the NMOS become strong, how will it affect the circuit? How about all the PMOS? How about if all the transistors were weak? Are you using any long-gate mosfets as a resistor for startup? This guy will definately change the VDD needed to start up, so you need to account for this when sizing your devices.

Another example, an LDO uses a PMOS pass device - the output current, load reg, etc will all change as the PMOS changes strong or weak. You will see this effect as you vary the corners - sometimes, you didn't realize a problem existed until one or more of the corner simulations shows a problem. Often, you can determine which type of transistor is the troublemaker, then find it more easily with those clues.

It's probably OK to design using typ-typ case as long as you understand how the circuit will change over temp and process, and verify all the corners. A lot of bad things happen at 125C, slow slow - it's a worst case, just like -40C, fast fast.

How about the monte carlo simulation...... what is the different compare to corner simulation...... both are predicting the yield if I not mistaken......
 

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ss sf fs ff

pbs681 said:
electronrancher said:
You have to care about all of them. When designing your circuit you should know how each transistor has been sized and placed to give a certain operation. If all the NMOS become strong, how will it affect the circuit? How about all the PMOS? How about if all the transistors were weak? Are you using any long-gate mosfets as a resistor for startup? This guy will definately change the VDD needed to start up, so you need to account for this when sizing your devices.

Another example, an LDO uses a PMOS pass device - the output current, load reg, etc will all change as the PMOS changes strong or weak. You will see this effect as you vary the corners - sometimes, you didn't realize a problem existed until one or more of the corner simulations shows a problem. Often, you can determine which type of transistor is the troublemaker, then find it more easily with those clues.

It's probably OK to design using typ-typ case as long as you understand how the circuit will change over temp and process, and verify all the corners. A lot of bad things happen at 125C, slow slow - it's a worst case, just like -40C, fast fast.

"""How about the monte carlo simulation...... what is the different compare to corner simulation...... both are predicting the yield if I not mistaken......"""


The difference in Monte Carlo analysis compared to Corner Analysis is the number of simulation you run to confirm the yield. In Monte Carlo analysis, you have to run a few hundred to thousand simulation in order to have more number of combination of processes and mismatches, whereby in Corner Analysis, you just need to run 5 simulation for SS,FF,FS,SF,TT. In this 5 simulation, what ever possibilities of process distribution is all ready taken into consideration.

Hope this helps you.
 

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what does ff top mean?

shaq said:
rajanarender_suram said:
Anachip said:
electronrancher said:
as montage said, they stand for typical, slow, and fast. since the transistors vary from lot to lot, we use these process corners to check the effects of process variation on our circuit. if you ask me, the main contributor is tox, which makes both transistor either slow or fast. it's fairly unusual to get sf or fs cases, because this means that something is affecting each type of transistor differently. one way this can happen is if the threshold adjust is too heavy or too light, making the vt of the devices unmatched. but that is pretty minor in my experience, usually the variation affects all devices at once - making them ss or ff..

btw - the combination sf means slow nmos and fast pmos (n is always first).

So, when talking about corner analysis, which one we have to care to most. Is it SS,FF or SF, FS?? Which process the design has to pass the most ? Thanks.

these are mos corners
TT: typical typical
FF:Fast nmos Fast pmos
SS:Slow nmos Slow pmos
FS:Fast nmos Slow pmos
SF:Slow nmos Fast pmos

All the corners have to be taken care for the better yeild.

my finding most of the time SS, 125C, low supply voltage(especially for feedback less ckt) is the most worst corner

Dear rajanarender_suram,

As you say, FF means fast nmos and fast pmos.

But, I have a little question that is what does the "Fast" mean?

Does it mean that tox is thinner than typical corner?


Actually what i know Fast in the sense is carrying higher currents than normal...
it is the variation of the process in such a way it carries higher current than typical.
and slow is vice versa
 

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mos ff ss tt

suria3 said:
pbs681 said:
electronrancher said:
You have to care about all of them. When designing your circuit you should know how each transistor has been sized and placed to give a certain operation. If all the NMOS become strong, how will it affect the circuit? How about all the PMOS? How about if all the transistors were weak? Are you using any long-gate mosfets as a resistor for startup? This guy will definately change the VDD needed to start up, so you need to account for this when sizing your devices.

Another example, an LDO uses a PMOS pass device - the output current, load reg, etc will all change as the PMOS changes strong or weak. You will see this effect as you vary the corners - sometimes, you didn't realize a problem existed until one or more of the corner simulations shows a problem. Often, you can determine which type of transistor is the troublemaker, then find it more easily with those clues.

It's probably OK to design using typ-typ case as long as you understand how the circuit will change over temp and process, and verify all the corners. A lot of bad things happen at 125C, slow slow - it's a worst case, just like -40C, fast fast.

"""How about the monte carlo simulation...... what is the different compare to corner simulation...... both are predicting the yield if I not mistaken......"""


The difference in Monte Carlo analysis compared to Corner Analysis is the number of simulation you run to confirm the yield. In Monte Carlo analysis, you have to run a few hundred to thousand simulation in order to have more number of combination of processes and mismatches, whereby in Corner Analysis, you just need to run 5 simulation for SS,FF,FS,SF,TT. In this 5 simulation, what ever possibilities of process distribution is all ready taken into consideration.

Hope this helps you.

Thanks.....
Anyway, since we already covered all the possibbilities of the process variation by running 5 corners simulation, why do we still need to run monte carlo. If we pass 5 corners requirement, then our chip should functioning within the specification right..... need your advise

Added after 9 minutes:

shaq said:
rajanarender_suram said:
Anachip said:
electronrancher said:
as montage said, they stand for typical, slow, and fast. since the transistors vary from lot to lot, we use these process corners to check the effects of process variation on our circuit. if you ask me, the main contributor is tox, which makes both transistor either slow or fast. it's fairly unusual to get sf or fs cases, because this means that something is affecting each type of transistor differently. one way this can happen is if the threshold adjust is too heavy or too light, making the vt of the devices unmatched. but that is pretty minor in my experience, usually the variation affects all devices at once - making them ss or ff..

btw - the combination sf means slow nmos and fast pmos (n is always first).

So, when talking about corner analysis, which one we have to care to most. Is it SS,FF or SF, FS?? Which process the design has to pass the most ? Thanks.

these are mos corners
TT: typical typical
FF:Fast nmos Fast pmos
SS:Slow nmos Slow pmos
FS:Fast nmos Slow pmos
SF:Slow nmos Fast pmos

All the corners have to be taken care for the better yeild.

my finding most of the time SS, 125C, low supply voltage(especially for feedback less ckt) is the most worst corner

Dear rajanarender_suram,

As you say, FF means fast nmos and fast pmos.

But, I have a little question that is what does the "Fast" mean?

Does it mean that tox is thinner than typical corner?

You can check the model file under section device...... it has all the parameters name that varies and how they define the variation...
 

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what does fs and ss mean

rajanarender_suram said:
pbs681 said:
suria3 said:
pbs681 said:
electronrancher said:
You have to care about all of them. When designing your circuit you should know how each transistor has been sized and placed to give a certain operation. If all the NMOS become strong, how will it affect the circuit? How about all the PMOS? How about if all the transistors were weak? Are you using any long-gate mosfets as a resistor for startup? This guy will definately change the VDD needed to start up, so you need to account for this when sizing your devices.

Another example, an LDO uses a PMOS pass device - the output current, load reg, etc will all change as the PMOS changes strong or weak. You will see this effect as you vary the corners - sometimes, you didn't realize a problem existed until one or more of the corner simulations shows a problem. Often, you can determine which type of transistor is the troublemaker, then find it more easily with those clues.

It's probably OK to design using typ-typ case as long as you understand how the circuit will change over temp and process, and verify all the corners. A lot of bad things happen at 125C, slow slow - it's a worst case, just like -40C, fast fast.

"""How about the monte carlo simulation...... what is the different compare to corner simulation...... both are predicting the yield if I not mistaken......"""


The difference in Monte Carlo analysis compared to Corner Analysis is the number of simulation you run to confirm the yield. In Monte Carlo analysis, you have to run a few hundred to thousand simulation in order to have more number of combination of processes and mismatches, whereby in Corner Analysis, you just need to run 5 simulation for SS,FF,FS,SF,TT. In this 5 simulation, what ever possibilities of process distribution is all ready taken into consideration.

Hope this helps you.

Thanks.....
Anyway, since we already covered all the possibbilities of the process variation by running 5 corners simulation, why do we still need to run monte carlo. If we pass 5 corners requirement, then our chip should functioning within the specification right..... need your advise


Monte carlo does mismatch simulations where as process corners doesnot....

This is true. Corner analysis does include all the process variation possiblities, whereby the Monte Carto Analysis will do both the process and mismatch analysis. So, even though your design pass the Corner Analysis for all the 5 cases, it is still a necessary for you to run Mismatch analysis in Monte Carlo to confirm on the mismatch matter for your design to behave. Thanks
 

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what does page 71 ff mean

[/quote]This is true. Corner analysis does include all the process variation possiblities, whereby the Monte Carto Analysis will do both the process and mismatch analysis. So, even though your design pass the Corner Analysis for all the 5 cases, it is still a necessary for you to run Mismatch analysis in Monte Carlo to confirm on the mismatch matter for your design to behave. Thanks[/quote]

I agree to suria...after even corner analysis mismatch analysis need to be performed for statistical variation of performance parameters of the designed block arising from device-,ismatch.....definitely the "Monte Carlo Method" does this.... some times it is time taking and not affordable....a preactical way of device mismatch simulation is given in the following link.....it is a commonly used method and not applicable for huge blocks...but good for blocks having low transistor count.....



hope would help u....

sankudey
 

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tt ff ss fs sf

This is true. Corner analysis does include all the process variation possiblities, whereby the Monte Carto Analysis will do both the process and mismatch analysis. So, even though your design pass the Corner Analysis for all the 5 cases, it is still a necessary for you to run Mismatch analysis in Monte Carlo to confirm on the mismatch matter for your design to behave. Thanks[/quote]

I agree to suria...after even corner analysis mismatch analysis need to be performed for statistical variation of performance parameters of the designed block arising from device-,ismatch.....definitely the "Monte Carlo Method" does this.... some times it is time taking and not affordable....a preactical way of device mismatch simulation is given in the following link.....it is a commonly used method and not applicable for huge blocks...but good for blocks having low transistor count.....

h**p://

hope would help u....

sankudey[/quote]

Thanks everybody.... now I understand
 

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condiciones ss sf fs ff

thast means the technology's envirnoment
 

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ff means

those are just different corners name that is ofen seen in model files
 

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what does sf mean?

FAST MOS : Smaller Vth
SLOW MOS : larger Vth
 
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low vt transistor

u have to check the ss ( slow slow corner) which is a real culprit in most of time ..
 

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