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What does .sdc file contain?

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vreddy

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can anyone explain me abt the detail info abt sdc file......

wat i know/:----sdc constraints has,

setup & hold time information, clk to every net, timing info for std cells, blocks, io pads..io delays & port pins,...............other than this anythin more??

wat abt false path, multi clk path it also conatins or not??

plz do correct me if i'm wrong

regards
 

uday_das

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Re: .sdc

Yes , SDC file contains timing exception paths i.e false path ( set_false_path ) , multicycle path ( set_multicycle_path ) which is used by downstream tool like STA tool etc.
 

rjainv

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.sdc

its a simplified format for passing timing exceptions understood by tools from various vendors...
It has only timing constraints and exceptions namely
1) clock definitions , source latency
2) IO delays
3) multicycle paths
4) max delays
5) false_paths
6) case analysis
 

vreddy

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.sdc

thanks jain,

but can u elaborate each of them.....

thanks in advance
 

rjainv

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Re: .sdc

1) clock definitions , source latency
all create_clocks/create_generated_clocks to define the clock sources
source latency is arrival of clock at the clock source point
2) IO delays
The input delay or output delay of signal at the ports of design.
3) multicycle paths
If there are multicycle paths in your design. This is to relax setup, and if applicable, relax hold requirements.

4) max delays
Instead of using clock period, give a max delay constraint as equivalent of setup check.
similarly there is a min delay constraint as equivalent of hold check.
There usage varies...
5) false_paths
Paths which by design are known to be static, or for the current analysis are don't cares... like test mode /configuration signals etc...
6) case analysis
To break the timing arcs which don't exist in design. This is like putting your chip in one of the possible operational modes. Like test mode/ mbist mode/ jtag mode or functional mode etc...
 

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